• The Journal of Society for e-Business Studies
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• v.2 no.1
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• pp.1-20
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• 1997

This study aims to suggest CALS implementation strategies and policies for information-based management of small and medium companies in Korea. At the turning point from traditional document-based management to recent digital-based one, it is well known that implementation of CALS concept is crucial for advancing business management of small and medium enterprises In order to attack the aim, this paper critically analyzes the empirical difficulties and obstacles of the current information-based management of small and medium companies in Korea. On the basis of the above analysis, this paper suggests the strategic plans and policies of CALS implementation for small and medium enterprises in Korea as follows. First, government should provide the supporting policies and proper system so that the large enterprise can be linked with small and medium companies for sharing necessary information. Second, similar enterprises should be integrated on the basis of information and automation evaluation. Third, implementation strategies and plans should be advanced on the basis of the informationalized phases with respect to the technology level of small and medium enterprises. For more efficient CALS implementation, this paper also proposes the following subsidiary policies. First, it is substantially important to publicize the nation-wide spreading of CALS mind. Second, it is strongly recommended to educate and train CALS specialist on a consistant basis. Third, government should support the enterprises by providing sufficient fund for CALS implementation. Fourth, the ideal CALS implementation models for small and medium enterprises should be developed. Fifth, the consulting and training program for CALS implementation should be established through ECRC (Electronic Commerce Resource Center). My study was based upon the enterprises' responses to the questionaires I made

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.3
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• pp.401-410
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• 2023

In this paper, we propose optimization methods for implementing SPARKLE, one of the NIST LWC finalists, on a 64-bit ARMv8 processor. The proposed methods consist of two approaches: an implementation using ARM A64 instructions and another using NEON ASIMD instructions. The A64-based implementation is optimized by performing register scheduling to efficiently utilize the available registers on the ARMv8 architecture. By utilizing the optimized A64-based implementation, we can achieve speeds that are 1.69 to 1.81 times faster than the C reference implementation on a Raspberry Pi 4B. The ASIMD-based implementation, on the other hand, optimizes data by parallelizing the ARX-boxes to perform more than three of them concurrently through a single vector instruction. While the general speed of the optimized ASIMD-based implementation is lower than that of the A64-based implementation, it only slows down by 1.2 times compared to the 2.1 times slowdown observed in the A64-based implementation as the block size increases from SPARKLE256 to SPARKLE512. This is an advantage of the ASIMD-based implementation. Therefore, the ASIMD-based implementation is more efficient for SPARKLE variant block cipher or permutation designs with larger block sizes than the original SPARKLE, making it a useful resource.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.25 no.3
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• pp.66-81
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• 2021

In this paper, we review the lowest order staggered discontinuous Galerkin methods on polygonal meshes in 2D. The proposed method offers many desirable features including easy implementation, geometrical flexibility, robustness with respect to mesh distortion and low degrees of freedom. Discrete function spaces for locally H¹ and H(div) spaces are considered. We introduce special properties of a sub-mesh from a given star-shaped polygonal mesh which can be utilized in the construction of discrete spaces and implementation of the staggered discontinuous Galerkin method. For demonstration purposes, we consider the lowest case for the Poisson equation. We emphasize its efficient computational implementation using only geometrical properties of the underlying mesh.

• Journal of Internet Computing and Services
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• v.20 no.3
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• pp.25-31
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• 2019

Along with the recent advances in quantum computers, it is anticipated that cryptographic attacks using them will make it insecure to use existing public key algorithms such as RSA and ECC. Currently, a lot of researches are underway to replace them by devising PQC (Post Quantum Cryptography) schemes. In this paper, we propose a performance enhancement method for Lizard implementation which is one of NIST PQC standardization submission. The proposed method is able to improve the performance by 7 ~ 25% for its algorithms compared to the implementation in the submission through the techniques of various implementation aspects. This study hopes that Lizard will become more competitive as a candidate for PQC standardization.

• Journal of Information Technology Services
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• v.7 no.3
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• pp.97-114
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• 2008

Many companies have implemented ERP systems to enhance their process competitiveness. Since most ERP systems down to date are implemented and managed on each separated business-unit or company level, such systems run short of the consideration about global business processes and global system managements. In order to integrate a successful global ERP, it is essential to apply the well-systematic implementation methodology which considers global standardization and global IT requirements. It is, however, the actual circumstance that such well-structured methodologies for global ERP implementation are hardly shown not only from domestic site but from foreign one. This paper indicates the global ERP implementation guideline with integrated approach including; the standard process design for efficient execution of global business; the ERP implementation method considering global IT requirements; and, the management method for global system operation. GSI ERP methodology is composed of 3 Phase：Global Strategy Planning, Global Template Construction and Global Roll-Out. Phase1; Global Strategy Planning contains Environment Analysis, GSI direction and Implementation Plan. Phase2; Global Template Construction contains Business blueprint, GSI operation design and Global template implementation. Phase3; Global Roll-out contains local business analysis, local ERP implementation and Global ERP Operation.

• Journal of information and communication convergence engineering
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• v.14 no.3
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• pp.177-183
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• 2016

A lot of Internet of Things devices has resource-restricted environment, so it is difficult to implement the existing block ciphers such as AES, PRESENT. By this reason, there are lightweight block ciphers, such as SIMON, SPECK, and Simeck, support various block/key sizes. These lightweight block ciphers can support the security on the IoT devices. In this paper, we propose efficient implementation methods and performance results for the Simeck family block cipher proposed in CHES 2015 on an 8-bit ATmega128-based STK600 board. The proposed methods can be adapted in the 8-bit microprocessor environment such as Arduino series which are one of famous devices for IoT application. The optimized on-the-fly (OTF) speed is on average 14.42 times faster and the optimized OTF memory is 1.53 times smaller than those obtained in the previous research. The speed-optimized encryption and the memory-optimized encryption are on average 12.98 times faster and 1.3 times smaller than those obtained in the previous studies, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.219-227
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• 2012

This paper describes the design and implementation of an efficient image security system for CCTV using the analysis technique of color informations. In conventional approaches, the compression and encryption techniques are mainly used for reducing the data size of the original images while the analysis technique of color information is first proposed, which eliminates the overlapping part of the original image data in our approach. In addition, security-enhanced CCTV image security system is presented using SSL/VPN tunneling technique. When we use the method proposed in this paper, an efficient image processing is enable for a mount of information, and also security problem is enhanced. Through the implementation results, the proposed method showed that the original image information are dramatically reduced.

• Journal of Engineering Education Research
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• v.4 no.1
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• pp.20-25
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• 2001

This paper presents the practical implementation methodology of a web-based Virtual Laboratory in the field of electrical and electronic engineering, in which efficient self-learning can be available due to high interactivities between a teacher and a learner. Now that the proposed Virtual Laboratory is composed of 3 learning classrooms and their management system, the learners can understand easily the several important electrical concepts and make an experiment in the cyberspace through simple mouse manipulations. The results of this research are to allow the implementation of an efficient Virtual Laboratory system, and are also expected to make a contribution to the activation of educational system in cyberspace.

• Journal of Information Processing Systems
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• v.8 no.1
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• pp.159-174
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• 2012

This paper presents a study on a high-performance design for a block cipher algorithm implemented on modern many-core graphics processing units (GPUs). The recent emergence of VLSI technology makes it feasible to fabricate multiple processing cores on a single chip and enables general-purpose computation on a GPU (GPGPU). The GPU strategy offers significant performance improvements for all-purpose computation and can be used to support a broad variety of applications, including cryptography. We have proposed an efficient implementation of the encryption/decryption operations of a block cipher algorithm, SEED, on off-the-shelf NVIDIA many-core graphics processors. In a thorough experiment, we achieved high performance that is capable of supporting a high network speed of up to 9.5 Gbps on an NVIDIA GTX285 system (which has 240 processing cores). Our implementation provides up to 4.75 times higher performance in terms of encoding and decoding throughput as compared to the Intel 8-core system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.37-44
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• 2010

New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC. However, these new features induce significant implementation complexity increases. In this paper, an efficient architecture for spiral-type motion estimation is proposed. First, we propose a hardware-friendly spiral search order. Then, an efficient processing element (PE) architecture for ME is proposed to achieve the proposed search order. The improved PE enables one-pixel-move of the reference pixel data to top, bottom, right, and left by four ports for input and output. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4x4 is introduced in the proposed architecture. As the result of hardware implementation, the hardware cost is about 145k gates. Maximum clock frequency is 134 MHz in the case of FPGA (Xilinx Vertex5) implementation.