• The Journal of Natural Sciences
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• v.7
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• pp.27-35
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• 1995

This paper introduces a VLSI (Very Large Scale Integrated Circuit) implementation of the 2-D Discrete Cosine Transform (DCT) with an application to image and video coding. This implementation, which is based upon a state space model, uses both algorithm and data partitioning to achieve high efficiency. With this implementation, the amount of data transfers between the processing elements (PEs) are reduced and all the data transfers are limitted to be local. This system accepts the input as a progressively scanned data stream which reduces the hardware required for the input data control module. With proper ordering of computations, a matrix transposition between two matrix by matrix multiplications, which is required in many 2-D DCT systems based upon a row-column decomposition, can be also removed. The new implementation scheme makes it feasible to implement a single 2-D DCT VLSI chip which can be easily expanded for a larger 2-D DCT by cascading these chips.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.423-431
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• 2021

SPECK and SIMON are lightweight block ciphers developed by NSA(National Security Agency), and SIMECK is a new lightweight block cipher that combines the advantages of SPECK and SIMON. In this paper, a large-capacity encryption using SPECK, SIMON, and SIMECK is implemented using a GPU with efficient parallel processing. CUDA library provided by NVIDIA was used, and performance was maximized by using CUDA assembly language PTX to eliminate unnecessary operations. When comparing the results of the simple CPU implementation and the implementation using the GPU, it was possible to perform large-scale encryption at a faster speed. In addition, when comparing the implementation using the C language and the implementation using the PTX when implementing the GPU, it was confirmed that the performance increased further when using the PTX.

• ETRI Journal
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• v.27 no.5
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1145-1147
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• 2013

There are two FFT(Fast Fourier Transform) algorithms, which are DIT(Decimation-In-Time) and DIF(Decimation-In- Frequency). Even the DIF algorithm is more widely used because of its various implementation architectures, the DIT structures have not been investigated. In this paper, the DIT Radix-4 algorithm is derived and its efficient butterfly structure is proposed for SoC(System on a Chip) implementation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• The Journal of Fisheries Business Administration
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• v.50 no.4
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• pp.45-57
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• 2019

Effective implementation of private subsidy projects requires comprehensive expertise in the aquaculture and construction sectors to be provided to private subsidy operators, local government officials and others involved in budget execution and settlement. Due to the strengthening of laws and systems related to the execution of state subsidies since 2015, the efficient implementation of private-sector grant projects has been difficult for delays in projects, cancellations, and conflicts with local governments from lack of prior awareness and understanding of related regulations. It is expected that the government will be able to activate the project by analyzing the current status and problems of each phase of project implementation for improving quality internalization of the project effects, as well as quantitative growth of the private sector subsidy project for environmentally friendly aquaculture development projects.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.197-208
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• 1996

A neural network-based PSRI(position, scale, and rotation invariant) feature extraction and ATR (automatic target recognition) system are proposed and an efficient parallel implementatio of the proposed system using multicomputer is also presented. In the proposed system, the scale and rotationinvariant features are extracted from the contour projection of the number of edge pixels on each of the concentric circles, which is input t the cooperative network. We proposed how to decide the optimum depth and the width of the parallel pipeline system for real time applications by modeling the proposed system into a parallel pipeline implementation method using transputers is also proposed. The implementation results show that we can extract PSRI features less sensitive to input variations, and the speedup of the proposed ATR system is about 7.55 for the various rotated and scaled targets using 8-node transputer system.

• The Journal of Society for e-Business Studies
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• v.2 no.1
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• pp.117-129
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• 1997

As the lifecycle of a product becomes shorter, the communication between a contractor and a supplier in product information has got more importance. The CITIS(Contractor Integrated Technical Information Service) is required to provide authorized users with access to both data and applications they need to complete a task for contract. With the growth of WWW, there has been much study for the use of WWW for the implementation of CALS. The WWW has been proved as an efficient tool for CALS implementation due to its of publicity, openness, and free accessibility. In this study, we suggest using WWW tools, here, an intranet tool, as a basis for the implementation of CITIS

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.1154-1158
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• 2003

Finite element analysis of welding processes, which entail phase evolution, heat transfer and deformations, is considered in this paper. Attention focuses on numerical implementation of the thermo-elastic-plastic constitutive equation proposed by Leblond in consideration of the transformation plasticity. Based upon the multiplicative decomposition of deformation gradient, hyperelastic formulation is employed for efficient numerical integration, and the algorithmic consistent moduli for elastic-plastic deformations including transformation plasticity are obtained in the closed form. The convergence behavior of the present implementation is demonstrated via a couple of numerical examples.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.3
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• pp.235-244
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• 2014

This article introduces recent trends in RHC (Receding Horizon Control), also known as MPC (Model Predictive Control), that has been well recognized in industry and academy as a systematic approach for optimal design and constraint management. Constrained and robust RHCs will be briefly reviewed with milestone results. Among the diverse developments and achievements of RHCs, implementation issues will be focused on, together with the latest applications. In particular, this article introduces results on how to solve a finite horizon open-loop optimal control problem in an efficient way, together with code generation for real-time execution and easy implementation. Instead of traditional applications such as refineries and petrochemical plants, this article highlights some selected emerging applications, such as energy management systems and mechatronics, that have resulted from state-of-the-art high performance computing power and advanced numerical schemes.