• International Journal of Computer Science & Network Security
• /
• v.21 no.3
• /
• pp.60-70
• /
• 2021

In this paper we study the problem of implementation of security issues of blue tooth, especially secure simple pairing, with the help of an efficient four user authenticated key (4UAK) for an elliptic curve cryptography (ECC). This paper also deals with the design, implement and performance evaluation of secure simple pairing (SSP) using an elliptic curve cryptography, such as Diffie Hellman protocol when four users are involved. Here, we also compute the best, worst and average case step counts (time complexities). This work puts forth an efficient way of providing security in blue tooth. The time complexity of O(n⁴) is achieved using Rabin Miller Primality methodology. The method also reduces the calculation price and light communication loads.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.18 no.1
• /
• pp.1-9
• /
• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.10
• /
• pp.1861-1871
• /
• 1994

This paper presents efficient real time software implementation methods for the grayscale morphological composite function processing (FP) system. The proposed method is based on a matrix representation of the composite FP system using a basis matrix composed of structuring elements. We propose a procedure to derive the basis matrix for composite FP systems with any grayscale structuring element (GSE). It is shown that composite FP operations including morphological opening and closing are more efficiently accomplished by a local matrix operation with the basis matrix rather than cascade operations, eliminating delays and requiring less memory storage. In the second part of this paper, a VLSI implementation architecture for grayscale morphological operators is presented. The proposed implementation architecture employs a bit-serial approach which allows grayscale morphological operations to be decomposed into bit-level binary operation unit for the p-bit grayscale singnal. It is shown that this realization is simple and modular structure and thus is suitable for VLSI implementation.

• ETRI Journal
• /
• v.42 no.4
• /
• pp.518-526
• /
• 2020

This paper presents an efficient hardware random-number generator based on a beta source. The proposed generator counts the values of "0" and "1" and provides a method to distinguish between pseudo-random and true random numbers by comparing them using simple cumulative operations. The random-number generator produces labeled data indicating whether the count value is a pseudo- or true random number according to its bit value based on the generated labeling data. The proposed method is verified using a system based on Verilog RTL coding and LabVIEW for hardware implementation. The generated random numbers were tested according to the NIST SP 800-22 and SP 800-90B standards, and they satisfied the test items specified in the standard. Furthermore, the hardware is efficient and can be used for security, artificial intelligence, and Internet of Things applications in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.10a
• /
• pp.531-534
• /
• 2010

In this paper, we introduce an efficient energy management using a notion of virtual energy system for shared solar-powered sensor network. Virtual energy system is an abstraction that allows sensor network applications on a node to reserve their own fractions of the shared solar cell and the shared rechargeable battery, hence achieving logically partition of a shared renewable power source with no change in design and implementation. Our results show that our design and implementation are reliable, lightweight and efficient, allowing proper isolation of energy consumption among applications.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.14 no.6
• /
• pp.313-319
• /
• 2019

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.

• Journal of IKEEE
• /
• v.17 no.4
• /
• pp.550-558
• /
• 2013

In this paper, we propose an efficient hybrid lighting management system implementation on multiple protocol. The proposed hybrid lighting management system was implemented by configured as the data display part for management and control of lighting device and the data conversion-processing part the communication part of gateway. The data were designed the DB to enable to storage in real-time, and implemented able to manage by real time wireless remote control and schedule setting. The proposed an efficient hybrid lighting management system, it was possible the real-time monitoring and remote lighting control by peristalsis with smart devices and portable PC etc., and it could be obtained reduction effect of energy and electricity, communication cost.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.5
• /
• pp.2680-2700
• /
• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11C
• /
• pp.1045-1051
• /
• 2003

The SOVA, which produces the soft decision value, can be used as a sub-optimum solution for concatenated codes such as turbo codes, since it is computationally efficient compared with the optimum MAP algorithm. In this paper, we propose an efficient implementation of the SOVA used for decoding turbo codes, by reducing the number of calculations for soft decision values and trace-back operations. In order to utilize the memory efficiently, the whole block of turbo codes is divided into several sub-blocks in the proposed algorithm. It is demonstrated that the proposed algorithm requires less computation than the conventional algorithm, while providing the same overall performance.

• Journal of Navigation and Port Research
• /
• v.28 no.8
• /
• pp.673-678
• /
• 2004

The ENC standard, S-57 Specification was established to exchange hydrographic data between it's users such as HOs ECDIS users, etc. The digital navigation chart which is produced according to the S-57 Specification is called an ENC(Electronic Navigational Chart) and the SENC(System ENC) is a by-product of ENC suitable for computer graphics system Even though the efficient structure of SENC is a key element of measuring ECDIS performance, the amount of papers about these topics are small compared with other research fields. In this paper, the author designed an efficient spatial data structure of SENC, called Mesh This paper also includes the implementation result of the 'Mesh' which displays SENC on computer screen.