• 한국정보과학회논문지:소프트웨어및응용
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• 제34권6호
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• pp.562-571
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• 2007

많은 연구들을 통해 수행 속력, 효율성, 용이성, 안전성을 위하여 메모리 관리 기법들을 개선시켰다. 그러한 방법들 중에서 지역별 메모리 관리 기법은 각각의 객체 할당 위치에서 따라 정해진 지역에 할당 시키고 그 지역이 제거된다면 그 곳에 할당된 모든 객체의 메모리를 반환하는 방법이다. 본 논문에서는 메모리 제약적인 환경에서 힙 메모리 사용량을 줄이기 위해 로컬 지역을 재사용하는 방법을 제시한다. 기본 아이디어는 현재 함수가 수행될 동안 사용하지 않는 상위 로컬 지역을 재사용하는 것이다. 이러한 방법을 사용함으로써 메모리 제약적인 환경에서 메모리의 한계를 극복할 수 있을 것이다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1098-1100
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• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• 한국통신학회논문지
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• 제27권5C호
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• pp.411-421
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• 2002

본 논문에서는 고속의 전송속도를 요구하는 근래의 디지털 통신시스템에서 그 필요성이 크게 증가 하고 있는 고속 비터비 복호기의 설계를 위한 새로운 생존경로 메모리 관리 방법과 하드웨어 구조를 제안한다. 제안된 방법은 k-개의 시작노드번호 결정회로를 독창적 방법으로 제어함으로써 복호를 시작할 수 있는 합병된 생존경로를 즉시 역추적할 수 있으며 기존의 생존경로 관리 방법들에 비하여 더 작은 크기의 생존경로 메모리와 더 짧은 처리지연시간을 갖는다. 또, 제안된 방법에서는 동작 속도가 똑같은 1개의 읽기 포인터와 1개의 쓰기 포인터 만이 필요하므로 기존의 방법들에서 요구되었던 복잡한 k-포트 메모리나 k-배 빠른 읽기 능력을 갖는 메모리를 사용할 필요가 없이 표준적인 이중포트 메모리 구조를 사용하여 생존경로 메모리를 용이하게 구현할 수 있다. 제안된 방법은 즉시 역추적을 위한 추가의 하드웨어를 요구하지만 고속의 처리속도가 필요한 비터비 복호기 구현에 기존 방법들 보다 더 우수하다.

• 의학교육논단
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• 제12권2호
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• pp.27-33
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• 2010

The purpose of this study was to review the definition of cognitive load (CL), the relationship between CL and instructional design, and to provide a viewpoint of CL in curriculum and instructional design in medical education. Cognitive load theory (CLT) makes use of three hypotheses about the structure of human memory: working memory (WM) is limited in terms of the amount of information it can hold, in contrast with WM, long term memory is assumed to have no limits and organizes information as schemata. CL indicates the mental load on the limitation of WM. CLT has been used to design instructional interventions that help to ease the learning process. Extraneous CL is related to irrelevant instructional interventions, while intrinsic CL is the complexity of the information itself. Germane CL is the cognitive process for acquiring schema formation. It is a necessary CL to achieve deeper comprehension and solve problems. The range of medical education includes complex, multifaceted and knowledge-rich domains with clinical skills and attitudes. Therefore, CLT may be used to guide instructional design in medical education in terms of decreasing extraneous CL, adjusting intrinsic CL and enhancing the germane CL.

• 한국정보과학회논문지:시스템및이론
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• 제30권9호
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• pp.461-476
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• 2003

메모리 병목현상의 완화와 구현상의 용이함으로 인해 NUMA 시스템이 지난 수년 동안 전형적인 다중 프로세서 시스템으로 자리를 잡아 왔다. 하지만 NUMA 시스템은 그 구조의 특성상 원격 메모리로의 접근 비율이 커질수록 응답 속도의 지연이 심화되므로, NUMA 시스템의 구현에 있어서 원격 캐쉬의 효율적인 설계를 요구한다. 본 논문에서는 보다 효율적인 원격 캐쉬의 설계를 목표로 하여, 원격 캐쉬 상에서 실제 응용 프로그램의 공유 단위(Granularity of Sharing)의 패턴을 분석하여 원격 캐쉬의 라인 사이즈를 실행 시간에 가상적으로 변화시킬 수 있는“다중 그레인 원격 캐쉬”방식을 제안한다. 그리고 이를 MINT를 통해 모델링한 후 시뮬레이션을 수행하고 그 결과를 분석한다. 시뮬레이션에서는 먼저 Profile-Based 방식을 이용하여 각 응용 프로그램별 최적의 원격 캐쉬 라인 사이즈를 찾아내고, 이를 이용하여 기존의 일반적인 NUMA 시스템에서의 원격 캐쉬와 본 논문에서 제안한 다중 그레인 원격 캐쉬와의 상호 비교를 통해 성능상의 차이점을 비교, 분석한다. 그 후 다중 그레인 원격 캐쉬가 시스템과 응용 프로그램간의 다양한 관계 속에서도 항상 최악의 경우를 피하면서 최적의 경우와 유사한 결과를 가짐을 보인다.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.310-318
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• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• 전자공학회논문지A
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• 제31A권10호
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• pp.21-30
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• 1994

We discussed the Distributed Control System's design on preface and analyzed time of the real-time communication by using designed system. The DCS proposed in this thesis was implemented to network file system having recovery advantage and shared memory method to access file system of a Remote Station with ease. Also, this system minimized the network delay-time by using the real-time VME147 board. In implemented DCS, the performance analysis of real-time process of a Remote Station was done to get the total time for reak-tune communication from a Remote Station to the Central Station after terminating of process. For the analysis of system performance, we experiented by three steps. Firstly, we measuredthe processing the of LOOP function that real-time CPU convertes to-2,500~10.000 values from the input data of the Analog Interface Card. Secondly, we measured the processing time of the LOGIC function and the LOOP function. Lastly, we measured total processing time for communication from a Remote Station to the Centrol Station.

• 디지털융복합연구
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• 제6권4호
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• pp.25-34
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• 2008

This study explores the component factors of innovation brand to build organizational culture of government ministries. A perception of organizational officers on innovation brand is ranked orderly by brand awareness(recognition, discrimination), brand loyalty (identification, ease of memory, meaning diffusion, reaction of customer needs), brand salience, brand knowledge and brand innovation. The results of factor analysis classify the component factors with factor1(brand awareness, brand loyalty) and factor2(brand innovation). This results indicate that the officers definitely recognize the value of innovation brand and brand identity. The brand discrimination and brand loyalty can also positively affect perception on brand innovation.

• 디지털융복합연구
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• 제7권2호
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• pp.1-12
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• 2009

This study explored which the component factors on innovation brand to building an organizational culture of government. The innovation brand perception of organizational officers are in order brand awareness(recognition, discrimination) and brand loyalty(identification, ease of memory, meaning diffusion, the reaction of customer needs), brand salience, brand knowledge and brand innovation. The result of Importance-Performance analysis are as follows. We can see that Brand loyalty have Quadrant I meaning good management implementation. Brand Knowledge have Quadrant II meaning concentrate improving. Brand Uniqueness have Quadrant III meaning improving. And Recognition, familiarity and salience have Quadrant IV meaning low relative importance and high performance. The Quadrant IV consider the cost and benefit of brand management.

• 한국전기전자재료학회논문지
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• 제17권2호
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• pp.178-183
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• 2004

PBT thin film was known to be a representative for the FeRAM devices because of its good ferroelectric proporties and the ease in fabricating the thin film. However, there have been several problems such as polarization fatigue and leakage current in memory devices with a PZT thin film. In this study, Sm-dolled PZT thin films were fabricated by the so1-gel method, and their ferroelectric and dielectric proportrics were compared as a function of Sm content. We investigated the effect of the Sm dopant on structural and electrical properties of PZT film. Sm-doped PZT thin films on the Pt/Ti/SiO$_2$/Si substrates have been prepared by a sol-gel method. The remanent polarization and coercive field decreased with increasing the concentration of Sm. The dielectric constant and dielectric loss decreased with Increasing Sm content. Sm-doped PZT thin films showed improved fatigue characteristics compared to the undoped PZT thin film.