• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.80-89
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• 2017

The classical approaches to detect cracks are performed by experienced inspection professionals by annotating the crack patterns manually. Because of each inspector's personal subjective experience, it is hard to guarantee objectiveness. To solve this issue, automated crack detection methods have been proposed however the methods are sensitive to image noise. Depending on the quality of image obtained, the image noise affect overall performance. In this paper, we propose crack detection method using a convolutional encoder-decoder network to overcome these weaknesses. Performance of which is significantly improved in terms of the recall, precision rate and F-measure than the previous methods.

• Korean Journal of Crystallography
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• v.6 no.2
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• pp.88-92
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• 1995

Higly pure silicon crystals with an almost perfect lattice structure constityte a powerful metrological tool. The streographic standard prohection for the (111) orientation of diamond structure found by the Laue method shows angles between net planes of 60°. This value is known to be certain to some 10-8 rad. We have made a six-faced silicon polygon, and the (220) lattice planes of the polygon act as a reference angular standard. The information of angles between lattice planes could be taken by the X-ray diffraction. The angle of the rotary encoder have been calibrated using the silicon angle standard. The X-ray optics was double crystal arrangement.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.5
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• pp.432-438
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• 2005

In this paper, the high precision position control of AC Servo motor for semiconductor equipment is studied. The control system was implemented using TI DSP TMS320F2812 which has 150 MIPS speed for next generation motor control. The controlled 100W PMSM motor has 2,500 ppr optical incremental encoder. The control system has speed controller and current controller to control the motor position. The encoder pulses are divided into 4 times, which has 10,000 ppr and the motor system has the position accuracy of 1/10,000. If the resolution of the encoder is increased, the resolution of the position control will be increased.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.289-293
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• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

• Journal of the Korean Institute of Intelligent Systems
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• v.21 no.3
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• pp.283-289
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• 2011

In this research a controller based on velocity estimator for a Wheeled Inverted Pendulum (WIP) is designed and various numerical simulation studies are carried out. The WIP has stable and unstable equivalent points. To Keep the unstable equilibrium point, a controller should control carefully the wheels persistently. There are angle, angular velocity, displacement, and velocity of the WIP for controller inputs. The velocity is obtained by differentiating the encoder signals from the motor and is subject to the resolution of the encoder. An improved velocity detection method is proposed based on low resolution encoder and velocity estimator. Various numerical simulations are carried out for showing the validation of the velocity estimator in case of the inclined road condition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2045-2049
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• 2008

In this paper, we propose an novel architecture for H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18 um process including SRAM memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1744-1750
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• 2008

As the computing and network technique move rm and spread widly, the usage of multimedia application becomes in general while the usage of text based application becomes low. Especially the application which treats the streaming media such as video or movie, one of multimedia data, holds a majority in the usage of computing. MPEG, one of the typical compression standard of streaming media, provides very high compression ratio so that general users could be close to the streaming media with easy usage. However, the encoding of MPEG requires lots of computing power and time. In the paper, we design and implement a parallel MPEG encoder with MPI in cluster envrionment to reduce the encoding time of MPEG.

• Journal of Korean Society for Quality Management
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• v.49 no.4
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• pp.569-579
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• 2021

Purpose: The purpose of this study is the time series analysis for predicting the yield of crops applicable to each farm using environmental variables measured by smart farms cultivating tomato. In addition, it is intended to confirm the influence of environmental variables using a deep learning model that can be explained to some extent. Methods: A time series analysis was performed to predict production using environmental variables measured at 75 smart farms cultivating tomato in two periods. An LSTM-based encoder-decoder model was used for cases of several farms with similar length. In particular, Dual Attention Mechanism was applied to use environmental variables as exogenous variables and to confirm their influence. Results: As a result of the analysis, Dual Attention LSTM with a window size of 12 weeks showed the best predictive power. It was verified that the environmental variables has a similar effect on prediction through wieghtss extracted from the prediction model, and it was also verified that the previous time point has a greater effect than the time point close to the prediction point. Conclusion: It is expected that it will be possible to attempt various crops as a model that can be explained by supplementing the shortcomings of general deep learning model.

• Phonetics and Speech Sciences
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• v.13 no.1
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• pp.45-51
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• 2021

End-to-end (E2E) automatic speech recognition (ASR) has achieved promising performance gains with the introduced self-attention network, Transformer. However, due to training time and the number of hyperparameters, finding the optimal hyperparameter set is computationally expensive. This paper investigates the impact of hyperparameters in the Transformer network to answer two questions: which hyperparameter plays a critical role in the task performance and training speed. The Transformer network for training has two encoder and decoder networks combined with Connectionist Temporal Classification (CTC). We have trained the model with Wall Street Journal (WSJ) SI-284 and tested on devl93 and eval92. Seventeen hyperparameters were selected from the ESPnet training configuration, and varying ranges of values were used for experiments. The result shows that "num blocks" and "linear units" hyperparameters in the encoder and decoder networks reduce Word Error Rate (WER) significantly. However, performance gain is more prominent when they are altered in the encoder network. Training duration also linearly increased as "num blocks" and "linear units" hyperparameters' values grow. Based on the experimental results, we collected the optimal values from each hyperparameter and reduced the WER up to 2.9/1.9 from dev93 and eval93 respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.1
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• pp.115-126
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• 1999

As the processing speed of communication and computer system has been improved, high speed data processing is required to correct error of data. In this paper, decoding algorithm which is applicable to the wireless communication system is proposed and encoder and decoder are designed by using the proposed decoding algorithm. We design the encoder and decoder by using the VHDL(VHSIC Hardware Description Language) and simulate the designed encoder and decoder by using V-system. Designed algorithm is synthesized by using synopsys tools and is made to one chip by means of XILINX XC4010EPC84-4. When 20MHz was used as the input clock, data arrival time was 29.20ns and data require time was 48.70ns.