• The Journal of the Acoustical Society of Korea
• /
• v.22 no.7
• /
• pp.592-602
• /
• 2003

This paper aims to describe the basic structure of novel object-based 3D audio broadcasting system To overcome current uni-directional audio broadcasting services, the object-based 3D audio broadcasting system is designed for providing the ability to interact with important audio objects as well as realistic 3D effects based on the MPEG-4 standard. The system is composed of 6 sub-modules. The audio input module collects the background sound object, which is recored by 3D microphone, and audio objects, which are recorded by monaural microphone or extracted through source separation method. The sound scene authoring module edits the 3D information of audio objects such as acoustical characteristics, location, directivity and etc. It also defines the final sound scene with a 3D background sound, which is intended to be delievered to a receiving terminal by producer. The encoder module encodes scene descriptors and audio objects for effective transmission. The decoder module extracts scene descriptors and audio objects from decoding received bistreams. The sound scene composition module reconstructs the 3D sound scene with scene descriptors and audio objects. The 3D sound renderer module maximizes the 3D sound effects through adapting the final sound to the listner's acoustical environments. It also receives the user's controls on audio objects and sends them to the scene composition module for changing the sound scene.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.1
• /
• pp.47-56
• /
• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.3
• /
• pp.79-89
• /
• 2011

Recent development of embedded processors makes it possible to play back video contents in real-time on portable devices. Because of their limited battery capacity and low computational performance, however, portable devices still have significant problems in real-time decoding of high quality or high resolution compressed video. Although previous approaches are successful in achieving complexity-scalable decoder by controlling computational complexity of decoding elements, they cause significant objective quality loss coming from mismatch between encoder and decoder. In this paper, we propose a selective B slice skip-decoding method to implement a low complexity video decoder. The proposed method performs selective skip decoding process of B slice which satisfies the proposed conditions. The skipped slices are reconstructed by simple reconstruction method utilizing adjacent reconstructed pictures. Experimental result shows that proposed method not only reduces computational complexity but also maintains subjective visual quality.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1C
• /
• pp.102-110
• /
• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.3C
• /
• pp.247-254
• /
• 2008

H.264 provides a good coding efficiency compared with existing video coding standards, H.263, MPEG-4, based on the use of multiple reference frame for variable block size motion estimation, quarter-pixel motion estimation and compensation, $4{\times}4$ integer DCT, rate-distortion optimization, and etc. However, many modules used to increase its performance also require H.264 to have increased complexity so that fast algorithms are to be implemented as practical approach. In this paper, among many approaches, fast mode decision algorithm by skipping variable block size motion estimation and spatial-predictive coding, which occupies most encoder complexity, is proposed. This approach takes advantages of temporal and spatial properties of fast mode selection techniques. Experimental results demonstrate that the proposed approach can save encoding time up to 65% compared with the H.264 standard while maintaining the visual perspectives.

• Journal of Broadcast Engineering
• /
• v.20 no.3
• /
• pp.388-397
• /
• 2015

High Efficiency Video Coding (HEVC)/H.265 is a new video coding standard which is known as high compression ratio compared to the previous standard, Advanced Video Coding (AVC)/H.264. Due to achievement of high efficiency, HEVC sacrifices the time complexity. To apply HEVC to the market applications, one of the key requirements is the fast encoding. To achieve the fast encoding, exploiting thread-level parallelism is widely chosen mechanism since multi-threading is commonly supported based on the multi-core computer architecture. In this paper, we implement both the Tile-level parallelism and the Frame-level parallelism for HEVC encoding on multi-core platform. Based on the implementation, we present two approaches in combining the Tile-level parallelism with Frame-level parallelism. The first approach creates the fixed number of tile per frame while the second approach creates the number of tile per frame adaptively according to the number of frame in parallel and the number of available worker threads. Experimental results show that both improves the parallel scalability compared to the one that use only tile-level parallelism and the second approach achieves good trade-off between parallel scalability and coding efficiency for both Full-HD (1080 x 1920) and 4K UHD (3840 x 2160) sequences.

• Journal of Broadcast Engineering
• /
• v.17 no.5
• /
• pp.756-764
• /
• 2012

In current HEVC, prediction pixels are finally calculated by linear-function interpolation on two reference pixels. It is hard to expect good performance on the case of occurring large difference between two reference pixels. This paper decides more accurate prediction pixel values than current HEVC using linear function. While existing prediction process only uses two reference pixels, proposed method uses DCT-IF. DCT-IF analyses frequency characteristics of more than two reference pixels in frequency domain. And proposed method calculates prediction value adaptively by using linear-function, DCT-IF and cubic-function to decide more accurate interpolation value than to only use linear function. Cubic-function has a steep slope than linear-function. So, using cubic-function is utilized on edge in prediction unit. The complexity of encoder and decoder in HM6.0 has increased 3% and 1%, respectively. BD-rate has decreased 0.4% in luma signal Y, 0.3% in chroma signal U and 0.3% in chroma signal V in average. Through this experiment, proposed adaptive intra prediction method using DCT-IF and cubic-function shows increased performance than HM6.0.

• Journal of Broadcast Engineering
• /
• v.17 no.5
• /
• pp.716-724
• /
• 2012

In this paper, we propose a fast decision method of maximum coding depth decision and reference frame selection in HEVC. To reduce computational complexity and encoding time of HEVC, two methods are proposed. In the first method, the maximum depth of each coding unit (CU) in a largest CU (LCU) is constrained by using the maximum coding depth used by adjacent LCUs based on the assumption that the spatial correlation is very high and rate-distortion (R-D) cost. And we constrain the number of reference pictures for prediction unit (PU) performing motion estimation by using the motion information of the upper depth PU. The proposed methods reduce computational complexity of the HEVC encoder by constraining the maximum coding depth and the reference frame. We could achieve about 39% computational complexity reduction with marginal bitrate increase of 1.2% in the comparison with HM6.1 HEVC reference software.

• Journal of Broadcast Engineering
• /
• v.16 no.1
• /
• pp.1-13
• /
• 2011

In this paper, we propose an adaptive in-loop filter to improve the coding efficiency. Recently, there are post-filter hint SEI and block-based adaptive filter control (BAFC) methods based on the Wiener filter which can minimize the mean square error between the input image and the decoded image in video coding standards. However, since the post-filter hint SEI is applied only to the output image, it cannot reduce the prediction errors of the subsequent frames. Because BAFC is also conducted with a deblocking filter, independently, it has a problem of high computational complexity on the encoder and decoder sides. In this paper, we propose the low-complexity adaptive in-loop filter (LCALF) which has lower computational complexity by using H.264/AVC deblocking filter, adaptively, as well as shows better performance than the conventional method. In the experimental results, the computational complexity of the proposed method is reduced about 22% than the conventional method. Furthermore, the coding efficiency of the proposed method is about 1% better than the BAFC.

• Journal of Broadcast Engineering
• /
• v.25 no.3
• /
• pp.346-352
• /
• 2020

Versatile Video Coding (VVC), a next-generation video coding standard that is in the final stage of standardization, has adopted various techniques to achieve more than twice the compression performance of HEVC (High-Efficiency Video Coding). VVC adopted Bi-prediction with CU-level Weight (BCW), which generates the final prediction signal with the weighted combination of bi-predictions with various weights, to enhance the performance of the bi-predictive inter prediction. The syntax element of the BCW index is adaptively coded according to the value of NoBackwardPredFlag which indicates if there is no future picture in the display order among the reference pictures. Such syntax structure for signaling the BCW index could violate the flexibility of video codec and cause the dependency issue at the stage of bitstream parsing. To address these issues, this paper proposes an efficient BCW weight signaling method which enables all weights and parsing without any condition check. The performance of the proposed method was evaluated with various weight searching methods in the encoder. The experimental results show that the proposed method gives negligible BD-rate losses and minor gains for 3 weights searching and 5 weights searching, respectively, while resolving the issues.