• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.39-46
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• 1997

In this paper, we propose an area-efficient architecture of a reed-solomon (RS) decoder/encoder for digital VCRs. The new architecture of the decoder/encoder targeted to reduce the circit size and decoding latency has the following two features. First, area-efficeincy has been significantly improved by sharing a functional block for encoding, modified syndrome computation, and erasure locator polynomial evaluation. Second, modified euclid's algorithms has been implemented by using a new architecture. Experimental results have showed that the decoder/encoder designed by using the proposed method has been implemented with 25% smaller sie over straight forware implementation based on the conventional method [1] and the decoding latency has been reduced.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.378-381
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• 2003

Efficient development of method on a performance evaluation for machine tools has been regarded as the most important work for accuracy and quality enhancement to every user and manufacturer. A evaluation method of accuracy for machine tools has been studied recently according to the rapid increase of interest in precision machine tools. To this point of view, the circular interpolation test of machine tools is recognized as the most useful method to distinguish a dynamic accuracy of NC machine tools by ISO and ANSI/ASME, etc. In this paper, we have studied and developed the form measurement system with grid encoder to analyse the final accuracy of NC machine tools. we have analyzed the servo system error and geometric error of NC machine tools through measuring a dynamic error signal by this system. and then we verified the experimental result and enhanced the reliability by means of comparing the characteristics of the developed system with the kinematic ball-bar system.

• International Journal of Precision Engineering and Manufacturing
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• v.9 no.3
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• pp.82-84
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• 2008

A surface encoder based on the Half-shaded square pattern (HSSP) is presented. The HSSP working as reference grid is composed of the straight lines which are easy to be fabricated and make measuring time short. Since the periodic cell is separated in ON/OFF by the $45^{\circ}$ straight line, the duration from the starting point of scanning to the first rising edge and the duty cycle of the pulse train vary with respect to the position of the starting point. And the relationship between X and Y position and the duration, and duty cycle is described in the simple linear equation. Therefore, it is possible to measure X and Y position with the measured duration and duty cycle without calculating load. Through the test set-up, the feasibility of the proposed surface encoder was verified. Also the future works for improvement of performance were suggested.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.303-309
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• 2016

This paper presents a channel-adaptive rate control algorithm for low delay video coding. The main goal of the proposed method is to adaptively use the unknown available channel bandwidth while reducing the end-to-end delay between encoder and decoder. The key idea of the proposed algorithm is for the status of the encoder buffer to indirectly reflect the mismatch between the available channel bandwidth and the generated bitrate. Hence, the proposed method fully utilizes the unknown available channel bandwidth by monitoring the encoder buffer status. Simulation results show that although the target bitrate mismatches the available channel bandwidth, the encoder efficiently adapts the given available bandwidth to improve the peak signal-to-noise ratio.

• Journal of IKEEE
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• v.18 no.4
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• pp.630-635
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• 2014

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.149-151
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• 1997

This paper proposed a new method for the measurement of optical encoder. So far several methods were used for the encoder measurements, there were noise problems and needed many space to realize it. Specially, it is more serious under the multi-motor system. In this paper, we adapted the PIC microcontroller and replaced the TTL logics with the PIC software. Therefore, the effects of noise can be reduced, and we can realize the measuring method for the optical encoder under multi-motor system within one millisecond time base.

• Journal of the Korea Computer Industry Society
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• v.2 no.9
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• pp.1183-1190
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.667-670
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• 2003

In a switched reluctance motor drive, it is important to synchronize the stator phase excitation with the rotor position, because the position of rotor is an essential information. In the high-speed region, switching angles are fluctuated back and forth out of\ the preset value, which is caused by the sampling period of the microprocessor. In this paper, a low cost analog encoder suitable for practical applications is proposed. The validity of the proposed analog encoder with a proper logic controller is verified from the experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.429-436
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• 1988

This paper presents a method of designing a Bit-Serial Reed-Solomon encoder using Berlekamp's Bit-Serial Multiplier Algorithm and the implementation of the (255, 223) Bit-Serial Reed-Solomon encoder using TTL logics. It is shown from these results that this encoder require substanitially less hardware than the convenional Reed-Solomon encoders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.123-129
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• 2006

In this paper, we concentrate on reducing the complexity for efficient encoder. We design structural LDPC code using circulant matrix and permutation matrix and eIRA code. It is possible to design low complex encoder by using shift register and differential encoder and interleaver than general LDPC encoder that use matrix multiplication operation. The code designed by this structure shows similar performance as random code. And the proposed codes can considerably reduce a number of XOR gates.