• 제목/요약/키워드: ECB

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The study on the Temperature Characteristics on Shield Moving ECB with PM for Application of Railway Vehicle (철도시스템 적용을 위한 영구자석형 Shield moving형 와전류 제동기의 온도 특성에 관한 연구)

  • Jung, Hwan-Su;Han, Kyung-Hee;Lee, Chang-Mu;Jang, Gil-Su
    • Proceedings of the KIEE Conference
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    • 2015.07a
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    • pp.1603-1604
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    • 2015
  • ECB(Eddy Current Brake)는 철도시스템의 고속에서 제동력을 안정적으로 나타낼 수 있어서 TGV, ICE, JR-500등과 같은 철도에서 사용되고 있다. 하지만 저속에서는 효율적이지 못하고, 전자석은 경량성에 대한 문제와 에너지를 소비한다는 단점을 가지고 있다. 이 논문에서는 제안된 영구자석형 Shield moving형 와전류 제동기를 사용하였다. 이 와전류 제동기는 Shield의 각을 이동하여 제동력을 조절할 수 있으며 영구자석을 이용함으로서 전자석의 단점을 보안하였다. 하지만 영구자석은 온도에 대해 영향을 받을 수 있으므로 온도 특성은 전류밀도(J(A/m2))와 자속밀도(T)를 'Ansoft Maxell'을 시뮬레이션하여 확인하였다.

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A Mode for Block Ciphers, with Untraceable Dynamic Keys (블록 암호알고리즘을 위한, 추적불가능한 동적 키를 갖는 연산모드)

  • 김윤정;조유근
    • Proceedings of the Korean Information Science Society Conference
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    • 1999.10c
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    • pp.285-287
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    • 1999
  • 블록 암호알고리즘에 대한 기존의 연산 모드들(ECB 또는 CBC 등)은, 각 블록에 대하여 동일한 키로 암호화를 수행한다. 이것은 침입자가 한번의 암호 요청만을 수행하여 많은 수의 평문/암호문 쌍을 얻을 수 있게 함으로써 차분해독법 등의 공격에는 안전성을 제공하지 않는다. 본 논문에서는 블록 암호 알고리즘을 위한 새로운 모드를 제안하는데, 이 모드에서는 암호화되는 각각의 블록이 서로 다른 키로 암호화되도록 함으로써 블록의 개수가 많아짐에 따라 안전성 면에서 상당한 이득을 얻게 된다. 각 블록을 위한 서로 다른 키를 생성하는 것이 추가 연산을 필요로 하지만, 제안하는 모드를 DES에 적용한 TDK(a mode for DEA with unTraceable Dynamic Keys)의 수행 시간을 pentium과 sun sparc 상에서 측정해 본 결과 ECB 모드와 거의 유사함을 알 수 있었다.

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Design and Analysis of Eddy-Current Braker for High-Speed Train (고속전철 와전류 제동장치 설계와 특성해석 및 실험)

  • 정수진;강도현;김동희
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.51 no.12
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    • pp.659-663
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    • 2002
  • The brake systems of high-speed train are to be equipped with three different brake systems, such as regenerative brake with regenerative feedback in driving car, a pneumatic disc brake, and non-contact linear eddy-current brake(ECB). The regenerative brake and the pneumatic disc brake are acting on the wheels. Their achievable braking force depends on the adhesive coefficient, which is influenced by the weather condition and speed, between the wheel and The linear eddy current brake gets an economical solution in the high-speed train because of the independence of the adhesive coefficient, no maintenance needed. and the good control characteristics. The braking force and the normal force of ECB for korean high-speed train are analysed by the 2D FEM(Finite Element Method). Finally the normal force is compared with the experiential values to verify the analysis.

VLSI Design OF Cryptographic Processor for SEED Encryption Algorithm (SEED 암호 알고리즘을 이용한 암호 프로세서의 VLSI 설계)

  • 정진욱;최병윤
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2000.08a
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    • pp.345-348
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    • 2000
  • 본 논문에서는 현재 우리나라 전자상거래 표준인 SEED 암호화 알고리즘을 하드웨어로 구현하였다. 이 암호화 프로세서는 유연성과 하드웨어 면적을 줄이기 위해 파이프라인이 없는 1 unrolled loop 구조를 사용하였다. 그리고 ECB, CBC, CFB, OFB의 4가지 모드를 모두 지원할 수 있도록 하였다. key computation은 오버헤드를 감소시키도록 precomputation 기법을 사용하였다. 또한, 데이타 입ㆍ출력 시 증가되는 처리시간을 제거하기 위하여 외부 입ㆍ출력 레지스터와 data 입ㆍ출력 레지스터를 분리하여 데이타 입ㆍ출력 연산이 암호 프로세서의 암호화 연산과 병행하여 처리되도록 하였다. 암호 프로세서는 0.25$\mu\textrm{m}$ CMOS 기술을 사용하여 검증하였고 gate수는 대략 29.3K gate 정도가 소요되었으며, 100 MHz ECB 모드에서 최고 237 Mbps의 성능을 보였다.

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CPLD Implementation of SEED Cryptographic Coprocessor (SEED 암호 보조 프로세서의 CPLD 구현)

  • Choi Byeong-Yoon;Kim Jin-Il
    • Journal of the Institute of Convergence Signal Processing
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    • v.1 no.2
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    • pp.177-185
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    • 2000
  • In this paper CPLD design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then each subround is executed using one clock. To improve clock frequency, online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. The cryptographic coprocessor is designed using Altera EPF10K100GC503-3 CPLD device and its operation is verified by encryption or decryption of text files through ISA bus interface. It consists of about 29,300 gates and performance of CPLD chip is about 44 Mbps encryption or decryption rate under 18 Mhz clock frequency and ECB mode.

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The problem resolution algorithm in ESP protocol (ESP 프로토콜에서의 문제점 보완 알고리즘)

  • Lee, Yeong-Ji;Kim, Tae-Yun
    • The KIPS Transactions:PartC
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    • v.9C no.2
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    • pp.189-196
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    • 2002
  • IPSec is a protocol which provides data encryption, message authentication and data integrity on public and open network transmission. In IPSec, ESP protocol is used when it needs to Provide data encryption, authentication and integrity in real transmission Packets. ESP protocol uses DES-CBC encryption mode when sender encrypts packets and receiver decrypts data through this mode IV is used at that tome. This vague has many risks of attack during transmission by attacker because it is transferred clean and opened. If IV value is modified, then decryption of ESP data is impossible and higher level information is changed. In this paper we propose a new algorithm that it encrpty IV values using DES-ECB mode for preventing IV attack and checks integrity of whole ESP data using message authentication function. Therefore, we will protect attacks of IV and data, and guarantee more safe transmission on the public network.

A Mechanism for the Secure IV Transmission in IPSec (IPSec에서 안전한 IV 전송을 위한 메커니즘)

  • Lee, Young-Ji;Park, Nam-Sup;Kim, Tai-Yun
    • Journal of KIISE:Information Networking
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    • v.29 no.2
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    • pp.156-164
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    • 2002
  • IPSec is a protocol which provides data encryption, message authentication and data integrity on public and open network transmission. In IPSec, ESP protocol is used when it needs to provide data encryption, authentication and Integrity In real transmission packets. ESP protocol uses DES-CBC encryption mode when sender encrypts packets and receiver decrypts data through this mode IV is used at that time. This value has many tasks of attack during transmission by attacker because it is transferred clean and opened. If IV value is modified, then decryption of ESP data is impossible and higher level information is changed. In this paper we propose a new algorithm that it encrypts IV values using DES-ECB mode for preventing IV attack and checks integrity of whole ESP data using message authentication function. Therefore, we will protect attacks of IV and data, and guarantee core safe transmission on the public network.

A Design of PRESENT Crypto-Processor Supporting ECB/CBC/OFB/CTR Modes of Operation and Key Lengths of 80/128-bit (ECB/CBC/OFB/CTR 운영모드와 80/128-비트 키 길이를 지원하는 PRESENT 암호 프로세서 설계)

  • Kim, Ki-Bbeum;Cho, Wook-Lae;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.6
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    • pp.1163-1170
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    • 2016
  • A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

High Performance Hardware Implementation of the 128-bit SEED Cryptography Algorithm (128비트 SEED 암호 알고리즘의 고속처리를 위한 하드웨어 구현)

  • 전신우;정용진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.1
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    • pp.13-23
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    • 2001
  • This paper implemented into hardware SEED which is the KOREA standard 128-bit block cipher. First, at the respect of hardware implementation, we compared and analyzed SEED with AES finalist algorithms - MARS, RC6, RIJNDAEL, SERPENT, TWOFISH, which are secret key block encryption algorithms. The encryption of SEED is faster than MARS, RC6, TWOFISH, but is as five times slow as RIJNDAEL which is the fastest. We propose a SEED hardware architecture which improves the encryption speed. We divided one round into three parts, J1 function block, J2 function block J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined one round into three parts, J1 function block, J2 function block, J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined it to make it more faster. G-function is implemented more easily by xoring four extended 4 byte SS-boxes. We tested it using ALTERA FPGA with Verilog HDL. If the design is synthesized with 0.5 um Samsung standard cell library, encryption of ECB and decryption of ECB, CBC, CFB, which can be pipelined would take 50 clock cycles to encrypt 384-bit plaintext, and hence we have 745.6 Mbps assuming 97.1 MHz clock frequency. Encryption of CBC, OFB, CFB and decryption of OFB, which cannot be pipelined have 258.9 Mbps under same condition.