• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.285-288
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• 2001

In this paper a design of cryptographic coprocessor which implements AES Rijndael algorithm is described. To achieve average throughput of 1 round per 5 clocks, subround pipelined scheme is applied. To apply the coprocessor to various applications, three key sizes such as 128, 192, 256 bits are supported. The cryptographic coprocessor is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology and consists of about 36, 000 gates. Its peak performance is about 512 Mbps encryption or decryption rate under 200 Mhz clock frequency and 128-bit key ECB mode(AES-128ECB).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• Journal of KIISE:Information Networking
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• v.33 no.1
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• pp.91-102
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• 2006

We analyze the performance of MAC-layer Reed-Solomon error recovery in the cdma2000 1xEV-DO Broadcast and Multicast Services (BCMCSs) environment, with respect to the size of the ECB (Error Control Block) and the air-channel condition, and establish the relationship between ECB size, error recovery capacity and service latency. From this we propose an adaptive error recovery scheme which adjusts the size of the ECB to reflect the environment of the mobile nodes so as to meet the required service quality (target bit error-rate), while reducing the latency of real-time applications. Extensive simulation results show the effectiveness of our approach compared to the current static scheme. Proposed adaptive schemes achieves near optimal solution with respect to service latency while satisfying the required service quality.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.11
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• pp.611-616
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• 1999

The introduction of the eddy current braking(ECB) system in HSRT(high speed railway train) is known to be advantageous, in that the system is independent on wheel-rail adhesion coefficient which is greatly affected by weather condition. It also minimize the maintenance of the brake system and does not require any additional electric energy because it is powered form the regenerated power at the time of the braking. In this study, the braking and attraction forces of the ECB are simulated by 2-D FEM and are experimentally verified on a down-scaled prototype. A control algorithm of the ECB is proposed to generate constant braking torque using linear variation of the reference current according to speed. Experimental results shows that the constant torque is generated over all operating speed region by developed control algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9B
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• pp.1609-1617
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• 2000

In this paper a design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then subround is executed for one clock. To improve clock frequency online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. Also to eliminate performance degradation due to data input and data output time between host computer and coprocesor, background input/output method is used. The cryptographic coprocessor is designed using $0.25{\mu}{\textrm}{m}$ CMOS technology and consists of about 29,300 gates. Its peak performance is about 237 Mbps encryption or decryption rate under 100 Mhz clock frequncy and ECB mode.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.510-514
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• 2009

This program was developed in Visual C + +, the Windows operating system has security features within the files and directories. File and directory security, encryption / decryption operations yirueojimyeo file security can be round, to know the value of the key and security password I need to know the directory is designed to be decrypted. In addition, ECB, CBC algorithm and 3DES, SEED algorithms and methods, and encryption. De0 can not run that created the file extension, as has been developed to allow for double security.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.206-209
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• 2004

We investigated response characteristics of liquid crystal display(LCD) with different operating mode of nematic liquid crystals (NLCs) such as $45^{\circ}$twist nematic (TN), $67.3^{\circ}$TN and ECB(electrical controlled birefringence) on a rubbed polyimide (PI) surface. The three kinds of LCD operating mode obtain stable EO performance. Low transmittances of the $45^{\circ}$TN and $67.3^{\circ}$TN cell on the rubbed PI surface were achieved by using low cell gap d. The fast response time of ECB cell among the three kinds of LCD operating mode was measured.