• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• Korean Journal of Materials Research
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• v.4 no.7
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• pp.759-766
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• 1994

Our investigation aimed to reduce the leakage current of $Ta_2O_5$ thin film capacitor by layering SnOz thin film layer under Ta thin film, thereby supplying extra oxygen ions from the $SnO_{2}$ underlayer to enhance the stoichiometry of $Ta_2O_5$ during the oxidation of Ta thin film. Tantalum was evaporated by e-beam or sputtered on p-Si wafers with various deposition temperatures and was oxidized by dry--oxygen at the temperatures between $500^{\circ}C$ and $900^{\circ}C$. Aluminum top and bottom electrodes were formed to make Al/$Ta_2O_5$/p-Si/Al or $Al/Ta_2O_5/SnO_2$p-Si/AI MIS type capacitors. LCR meter and pico-ammeter were used to measure the dielectric constants and leakage currents of the prepared thm film capacitors. XRD, AES and ESCA were employed to confirm the crystallization of the thin f~lm and the compositions of the films. Dielectric constant of $Ta_2O_5$ thin film capacitor with $SnO_{2}$ underlayer was found to be about 200, which is about 10 times higher than that of $Ta_2O_5$ thin film capacitor without $SnO_{2}$ underlayer. In addition, higher oxidation temperatures increased the dielectric constants and reduced the leakage current. Higher deposition temperature generally gave lower leakage current. $Ta_2O_5/SnO_2$ capacitor deposited at $200^{\circ}C$ and oxidized at $800^{\circ}C$ showed significantly lower leakage current, $10^{-7}A/\textrm{cm}^2$ at $4 \times 10^{5}$V/cm, compared to the one without $SnO_{2}$ underlayer. XRD showed that $Ta_2O_5$ thin film was crystallized above $700^{\circ}C$. AES and ESCA showed that initially the $SnO_{2}$, underlayer supplied oxygen ions to oxidize the Ta layer, however, Sn also diffused into the Ta thin film layer to form a new $Ta_xSn_YO_Z$ , ternary oxide layer after all.

• Journal of the Korean Magnetics Society
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• v.13 no.5
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• pp.187-192
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• 2003

The magnetic and thermal properties of NiFe/[IrMn-Mn]/CoFe with Mn additions have been studied. As-deposited CoFe pinned layers with [IrMn-Mn]layer had dominantly larger exchange biasing field ( $H_{ex}$) and blocking temperature ( $T_{b}$) than those with pure I $r_{22}$M $n_{78}$ used. The $H_{ex}$ and $T_{b}$ improved with 76.8-78.1 vol% Mn, but those of the NiFe/IrMn/CoFe dropped considerably with more addition of 0.6 vol % Mn. The average x-ray diffraction peak ratios of fcc [(111)CoFe, NiFe]/(111)IrM $n_3$ textures for the Mn inserted total vol of 75.5, 77.5, and 79.3% were about 1.4, 0.8, and 0.6, respectively. For the sample without Mn inserted layer, the $H_{ex}$ between IrMn and CoFe layers was almost zero, but it increased to 100 Oe after annealing of 250 $^{\circ}C$. For as-grown two multilayers samples with ultra-thin Mn layers of 77.5 and 78.7 vol %, the $H_{ex}$s were 259 and 150 Oe, respectively. In case of IrMn with 77.5 vol% Mn, the $H_{ex}$ was increased up to 475 Oe at 350 $^{\circ}C$ but decreased to 200 Oe at 450 $^{\circ}C$, respectively. The magnetic properties and thermal stabilities of NiFe/[IrMn-Mn]/CoFe multilayer were enhanced with Mn additions. In applications where higher $H_{ex}$ and $T_{b}$ are required, proper contents of Mn can be used. be used. used.