• Geotechnical Engineering
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• v.12 no.2
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• pp.19-32
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• 1996

Based on Trifuilac's empirical model to transform earthquake acceleration time history in the time domain into Fourier amplitude spectrum in the frequency domail an earthquake scaling technique for simulating the earthquake record of certain magnitude as the required magnitude earthquake was suggested. Also, using the earthquake record of magni dude(M) 5.8, the simulated earthquake of magnitude(M) 8.0 was established and its application to dynamic testing system was proposed. The earthquake scaling technique could be considered by several terms : earthquake magnitude(M), earthquake intensity(MMI), epicentral distance, recording site conditions, component direction and confidence level required by the analysis. Albo, it had an application to the various earthquake records. The simulated earthquake in this study was established by two orthogonal horizontal components of earthquake acceleration-time history. The simulated earthquake shaking could be applied to the dynamic pile load test for the model tension pile and the model compressive open -ended piles driven into the pressure chamber. In the static pile load test, behavior of two piles was very different and after model tension pile experienced 2 or 3 successive slips of the pile relative to the soil, it was failed completely. During the simulated earthquake shaking, dynamic behavior and pile capacity degradation of two piles were very different.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.586-594
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• 2014

Maximizing the operating time by reducing the power consumption is important factor to operate sensor network under water networks. For efficient power consumption, dynamic voltage scaling method is available. This method operates low frequency when there is no workload. In case of abundant workload, high frequency operation completes hard work within short time, reducing power consumption. For this reason, complex cryptography should be computed in high frequency. In this paper, we apply dynamic voltage scaling method to cryptography and show performance evaluation. With this result, we can reduce power consumption for cryptography in under water communication.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.222-229
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• 2020

Recent multi-core processors for smart devices use per-core dynamic voltage and frequency scaling (DVFS) that enables independent voltage and frequency control of cores. However, because the conventional task scheduler was originally designed for per-core DVFS disabled processors, it cannot effectively utilize the per-core DVFS and simply allocates tasks evenly across all cores to core utilization with the same CPU frequency. Hence, we propose a novel task scheduler to effectively utilize percore DVFS, which enables each core to have the appropriate frequency, thereby improving performance and decreasing energy consumption. The proposed scheduler classifies applications into two types, based on performance-sensitivity and allows a performance-sensitive application to have a dedicated core, which maximizes core utilization. The experimental evaluations with a real off-the-shelf smart device showed that the proposed task scheduler reduced 13.6% of CPU energy (up to 28.3%) and 3.4% of execution time (up to 24.5%) on average, as compared to the conventional task scheduler.

• Journal of Information Processing Systems
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• v.7 no.1
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• pp.93-102
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• 2011

In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.428-430
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.544-546
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.96-104
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• 2009

In the real system environments, the performance of the application is not linearly proportional to the clock frequency of the microprocessor, in contrast to the general assumption of conventional dynamic voltage scaling. In this paper, we analytically model the relation between the performance of the application and the clock frequency of the microprocessor, and introduce the energy-optimal scheduling algorithm for a task set with distinct application characteristics. In addition, we present a theorem for the energy-optimal scheduling, which the derivative of the energy consumption with respect to the execution time should be the same for all the tasks. The proposed scheduling algorithm always generates the energy-optimal scaling factor thanks to the theorem for energy-optimal scheduling. We achieved about 7% additional energy reduction in the experiments using synthetic task sets.