• Journal of Computing Science and Engineering
• /
• v.6 no.1
• /
• pp.26-38
• /
• 2012

Java has been increasingly used in programming for real-time systems. However, some of Java's features such as automatic memory management and dynamic compilation are harmful to time predictability. If these problems are not solved properly then it can fundamentally limit the usage of Java for real-time systems, especially for hard real-time systems that require very high time predictability. In this paper, we propose to exploit multicore computing in order to reduce the timing unpredictability that is caused by dynamic compilation and adaptive optimization. Our goal is to retain high performance comparable to that of traditional dynamic compilation, while at the same time, obtain better time predictability for Java virtual machine (JVM). We have studied pre-compilation techniques to utilize another core more efficiently, preoptimization on another core (PoAC) scheme to replace the adaptive optimization system (AOS) in Jikes JVM and the counter based optimization (CBO). Our evaluation reveals that the proposed approaches are able to attain high performance while greatly reducing the variation of the execution time for Java applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.755-758
• /
• 2016

In this paper, binary in the program function is to be called binary explain the function in any way to call with in the binary. And the functions required during the call to the elements and their dynamic links in the compilation process and its elements and C-language file describes the concept of 'linker' that connects, and static links and dynamic link Compare analysis differences. Also Do an experiment on Return To Dynamic Linker exploit.

• Journal of Computing Science and Engineering
• /
• v.6 no.2
• /
• pp.105-118
• /
• 2012

We propose two new approaches that automatically parallelize Java programs at runtime. These approaches, which rely on run-time trace information collected during program execution, dynamically recompile Java byte code that can be executed in parallel. One approach utilizes trace information to improve traditional loop parallelization, and the other parallelizes traces instead of loop iterations. We also describe a cost/benefit model that makes intelligent parallelization decisions, as well as a parallel execution environment to execute parallelized programs. These techniques are based on Jikes RVM. Our approach is evaluated by parallelizing sequential Java programs, and its performance is compared to that of the manually parallelized code. According to the experimental results, our approach has low overheads and achieves competitive speedups compared to the manually parallelizing code. Moreover, trace parallelization can exploit parallelism beyond loop iterations.

• Proceedings of the Korea Multimedia Society Conference
• /
• 2012.05a
• /
• pp.113-115
• /
• 2012

스마트폰은 다양한 서비스를 위한 기술이 집약되어 있으며 그 중 NFC(근거리 무선 통신) 기술은 기존의 모바일 RFID 기술보다 진일보하여 태그 읽기/쓰기 기능을 비롯하여 모바일 결제에 이르기까지 활용 범위가 매우 넓다. 이러한 NFC 기술을 활용한 안드로이드 어플리케이션의 구동에 있어 실시간 처리의 효율성은 서비스의 안정성에 크게 영향을 미친다. 따라서 안드로이드 플랫폼에서 보다 안정적인 실시간 서비스 실행을 위해 기존 안드로이드 실시간 처리 영역인 Dalvik VM의 동적 컴파일 메커니즘과 현재 발표되어 있는 개선된 방식의 메커니즘을 분석 정리하고자 한다. 또한 이를 바탕으로 향후 스마트 폰의 NFC 구동에 있어 Dalvik VM의 보다 최적화된 컴파일 방식을 제안할 수 있도록 연구하고자 한다.

• Journal of KIISE
• /
• v.41 no.11
• /
• pp.892-899
• /
• 2014

Dynamic binary instrumentation is a code insertion technique for debugging a program without scattering its execution flow, while the program is running. Most dynamic instrumentations are implemented using dynamic binary translation techniques. Existing studies translated program codes dynamically by parsing the machine code stream to intermediate representation (IR) and then applying compilation techniques for IRs. However, they have high overhead during translation, which is a major cause of difficulty in applying the dynamic binary translation technique to the program which requires high responsiveness. In this paper, we introduce a light-weight dynamic binary instrumentation framework based on a novel dynamic binary translation technique which has low overhead while translating the program code. In order to reduce the translation overhead, our approach adopts a tabular-based address translation and exploits a translation bypassing scheme, which stores the translated address of a frequently called library function in advance. It then accesses the translated address and executes function codes without code translation when calling the function. Our experiment results demonstrated that the proposed approach outperforms the prior dynamic binary translation techniques from 2% up to 65%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.1
• /
• pp.18-22
• /
• 2006

Epitaxial aluminum nitride films on 6H-SiC (0001) were fabricated using reactive RF magnetron sputtering and post-deposition rapid thermal annealing. The electrical properties of AIN films depending on film thickness and measurement temperature have been observed. Full width at half maximum of AIN (0002) was $0.1204^{\circ}$ (about 430 arcsec) X-ray rocking curve results. The equivalent oxide thickness (EOT) of AIN film was estimated as about 10 nm and the leakage current density was within the order of $10^{-8} 4/cm^2$. The dielectric constant of AIN film estimated from the accumulation region of C-V curve measured at $300^{\circ}C$ was 8.3. The dynamic dielectric constant was obtained as 5.1 from J vs. 1/T plots at the temperature ranging from R.T. to $300^{\circ}C$ From above, estimation temperature dependance of the electrical properties of Al/AIN/SiC MIS devices was affirmed and useful data compilation for the reliabilities of SiC MIS is expected.

• ETRI Journal
• /
• v.18 no.4
• /
• pp.265-286
• /
• 1997

This paper presents a new software development environment that supports an integrated methodology for covering all phases of software development and gives integrated methods with tools for ITUT (Telecommunication Standardization Section of the International Telecommunication Union) languages. The design of the environment to improve software productivity and quality is based on five main concepts: 1) formal specifications based on SDL (Specification and Description Language) and MSC (Message Sequence Charts) in the design phase, 2) verification and validation of those designs by tools, 3) automatic code generation and a safe separate compilation scheme based on CHILL (CCITT High-Level Language) to facilitate programming-in-the-many and programming-in-the-large. 4) debugging of distributed real-time concurrent CHILL programs, and 5) simulation of application software for integrated testing on the host machine based on CHILL. The application results of the environment compared with other approaches show that the productivity is increased by 19 % because of decreasing implementation and testing cost, and the quality is increased by 83 % because of the formal specifications with its static and dynamic checking facilities.

• Journal of KIISE:Software and Applications
• /
• v.32 no.7
• /
• pp.683-692
• /
• 2005

Java specification states that all accesses to an object must be checked at runtime if object refers to null. Since Java is an object-oriented language, object accesses are frequent enough to make null pointer checks affect the performance significantly. In order to reduce the performance degradation, there have been attempts to remove redundant null pointer checks. For example, in a Java environment where a just-in-time (JIT) compiler is used, the JIT compiler removes redundant null pointer check code via code analysis. This paper proposes a technique to remove additional null pointer check code that could not be removed by previous JIT compilation techniques, via early null pointer check using an architectural feature called predication. Generally, null point check code consists of two instructions: a compare and a branch. Our idea is moving the compare instruction that is usually located just before an use of an object, to the point right after the object is defined so that the total number of compare instructions is reduced. This results in reduction of dynamic and static compare instructions by 3.21$\%$ and 1.98$\%$. respectively, in SPECjvm98 bechmarks, compared to the code that has already been optimized by previous null pointer check elimination techniques. Its performance impact on an Itanium machine is an improvement of 0.32$\%$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.10
• /
• pp.85-94
• /
• 2004

In this paper, a register allocation techlique that translates memory accesses to register accesses Is presented to enhance embedded software performance. In the proposed method, a source code is profiled to generate a memory trace. From the profiling results, target functions with high dynamic call counts are selected, and the proposed register allocation technique is applied only to the target functions to save the compilation time. The memory trace of the target functions is searched for the memory accesses that result in cycle count reduction when replaced by register accesses, and they are translated to register accesses by modifying the intermediate code and allocating Promotion registers. The experiments where the performance is measured in terms of the cycle count on MediaBench and DSPstone benchmark programs show that the proposed method increases the performance by 14% and 18% on the average for ARM and MCORE, respectively.

• The KIPS Transactions:PartA
• /
• v.11A no.5
• /
• pp.373-382
• /
• 2004

In this paper, a register promotion technique that translates memory accesses to register accesses is presented to enhance embedded software performance. In the proposed method, a source code is profiled to generate a memory trace. From the profiling results, target functions with high dynamic call counts are selected, and the proposed register promotion technique is applied only to the target functions to save the compilation time. The memory trace of the target functions is searched for the memory accesses that result in cycle count reduction when replaced by register accesses, and they are translated to register accesses by modifying the intermediate code and allocating promotion registers. The experiments on MediaBench and DSPstone benchmark programs show that the proposed method increases the performance by 14% and 18% on the average for ARM and MCORE, respectively.