• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1A
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• pp.7-16
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• 2003

Handover is very important to support the mobility of user because wireless ATM networks have smaller cell size such as micro/pico cell for broadband mobile multimedia service In this paper, we propose dynamic path reservation handover scheme for fast inter-MSC (Mobile Switching Center) handovers To reduce the handover delay for connection re-routing, the proposed scheme reserves virtual channels from nearest common node to neighbor MSC in advance Especially, our handover scheme predicts the number of inter-MSC handover calls at each period by the prediction algorithm and reserve virtual channels The simulation and analysis results show that our scheme reduce handover complexity and has higher reservation channel utilization, compared with DVCT scheme.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.1
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• pp.146-170
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• 2017

Joint channel assignment and routing is a well-known problem in multi-radio wireless mesh networks for which optimal configurations is required to optimize the overall throughput and fairness. However, other objectives need to be considered in order to provide a high quality service to network users when it deployed with high traffic dynamic. In this paper, we propose a re-configuration optimization model that optimizes the network throughput in addition to reducing the disruption to the mesh clients' traffic due to the re-configuration process. In this multi-objective optimization model, four objective functions are proposed to be minimized namely maximum link-channel utilization, network average contention, channel re-assignment cost, and re-routing cost. The latter two objectives focus on reducing the re-configuration overhead. This is to reduce the amount of disrupted traffic due to the channel switching and path re-routing resulted from applying the new configuration. In order to adapt to traffic dynamics in the network which might be caused by many factors i.e. users' mobility, a centralized heuristic re-configuration algorithm called State-Aware Joint Routing and Channel Assignment (SA-JRCA) is proposed in this research based on our re-configuration model. The proposed algorithm re-assigns channels to radios and re-configures flows' routes with aim of achieving a tradeoff between maximizing the network throughput and minimizing the re-configuration overhead. The ns-2 simulator is used as simulation tool and various metrics are evaluated. These metrics include channel-link utilization, channel re-assignment cost, re-routing cost, throughput, and delay. Simulation results show the good performance of SA-JRCA in term of packet delivery ratio, aggregated throughput and re-configuration overhead. It also shows higher stability to the traffic variation in comparison with other compared algorithms which suffer from performance degradation when high traffic dynamics is applied.

• Convergence Security Journal
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• v.12 no.1
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• pp.35-42
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• 2012

Increase of data traffic and the advent of new real-time services require to change from the traditional TDM-based (Time Division Multiplexing) networks to the optical networks that soft and dynamic configuration. Voice and lease line services are main service area of the traditional TDM-based networks. This optical network became main infrastructure that offer many channel that can convey data, video, and voice. To provide high resilience against failures, Packet-optical networks must have an ability to maintain an acceptable level of service during network failures. Fast and resource optimized lightpath restoration strategies are urgent requirements for the near future Packet-optical networks with a Generalized Multi-Protocol Label Switching(GMPLS) control plane. The goal of this paper is to provide packet-optical network with a hierarchical multi-layer recovery in order to fast and coordinated restoration in packet-optical network/GMPLS, focusing on new implementation information. The proposed schemes do not need an extension of optical network signaling (routing) protocols for support.

• Journal of Biomedical Engineering Research
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• v.25 no.4
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• pp.269-275
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• 2004

Different biological tissues have different values of electrical resistivity. In EIT (electrical impedance tomography), we try to provide cross-sectional images of a resistivity distribution inside an electrically conducting subject such as the human body mainly for functional imaging. However, it is well known that the image reconstruction problem in EIT is ill-posed and the quality of a reconstructed image highly depends on the measurement error. This requires us to develop a high-performance EIT system. In this paper, we describe the development of a 16-channel digital EIT system including a single constant current source, 16 voltmeters, main controller, and PC. The system was designed and implemented using the FPGA-based digital technology. The current source injects 50KHz sinusoidal current with the THD (total harmonic distortion) of 0.0029% and amplitude stability of 0.022%. The single current source and switching circuit reduce the measurement error associated with imperfect matching of multiple current sources at the expense of a reduced data acquisition time. The digital voltmeter measuring the induced boundary voltage consists of a differential amplifier, ADC, and FPGA (field programmable gate array). The digital phase-sensitive demodulation technique was implemented in the voltmeter to maximize the SNR (signal-to-noise ratio). Experimental results of 16-channel digital voltmeters showed the SNR of 90dB. We used the developed EIT system to reconstruct resistivity images of a saline phantom containing banana objects. Based on the results, we suggest future improvements for a 64-channel muff-frequency EIT system for three-dimensional dynamic imaging of bio-impedance distributions inside the human body.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.44-51
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• 2008

A stereo audio digital-to-analog converter (DAC) with a power amplifier using asymmetric pulse-width modulation (PWM) is presented. To adopt class-D amplifier mainly used in high-power audio appliances for head-phones application, this work analyzes the noise caused by the inter-channel interference during the integration and optimizes the design of the sigma-delta modulator to decrease the performance degradation caused by the noise. The asymmetric PWM is implemented to reduce switching noise and power loss generated from the power amplifier. This proposed architecture is fabricated in 0.13-mm CMOS technology. The proposed audio DAC including the power amplifier with single-ended output achieves a dynamic range (DR) of 95-dB dissipating 4.4-mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.29-35
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• 2016

We have demonstrated a $Ti:LiNbO_3$ electro-optic electric-field sensors utilizing a $1{\times}2$ Y-fed balanced-bridge Mach-Zehnder interferometric (YBB-MZI) modulator which uses a 3-dB directional coupler at the output and dipole patch antenna. The operation and design were proved by the BPM simulation. A dc switching voltage of ~16.6 V and an extinction ratio of ~14.7 dB are observed at a wavelength of $1.3{\mu}m$. For a 20 dBm rf power, the minimum detectable electric-fields are ~1.12 V/m and ~3.3 V/m corresponding to a dynamic range of about ~22 dB and ~18 dB at frequencies 10 MHz and 50 MHz, respectively. The sensors exhibit almost linear response for the applied electric-field intensity from 0.29 V/m to 29.8 V/m.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.60-67
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• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.