• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.28 no.2
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• pp.233-237
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• 2010

The recent advance of sensor networks and ubiquitous techniques allow collecting and analyzing of the data which overcome the limitation imposed by time and space in real-time for making decisions. Also, analysis and prediction of collected data can support useful and necessary information to users. The collected data in sensor networks environment is the stream data which has continuous, unlimited and sequential properties. Because of the continuous, unlimited and large volume properties of stream data, managing stream data is difficult. And the stream data needs dynamic processing method because of the memory constraint and access limitation. Accordingly, we analyze correlation stream data using principal component analysis. And using result of analysis, it helps users for making decisions.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.206-209
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• 2014

Control message exchange is major job for cognitive radio to exist and use spectrum opportunistically. For this control message exchange they need a common control channel (CCC). Once this channel is affected by a primary user, communication stops until new CCC is setup. This takes substantial time and if they could not get free channel, this halt continues for long time. To prevent such cease of communication, we propose a combination of two networks, namely WLAN and UWB, to let the communication continue. In our proposed idea if the CCC of a certain CR in WLAN is affected, the CR changes its network from WLAN to UWB and keeps the communication because UWB cannot be affected by PU. In the proposed idea every cognitive radio has two transceivers; one for the overlay network (WLAN) and another UWB network. If a primary user is detected in the spectrum of a cognitive radio, it continues exchanging control messages under the UWB network and in parallel negotiates for a new CCC using the WLAN network. This idea solves the communication interruption until new CCC is setup.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.75-84
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• 2005

This research is to design a high performance NAND-type flash memory package with a smart buffer cache that enhances the exploitation of spatial and temporal locality. The proposed buffer structure in a NAND flash memory package, called as a smart buffer cache, consists of three parts, i.e., a fully-associative victim buffer with a small block size, a fully-associative spatial buffer with a large block size, and a dynamic fetching unit. This new NAND-type flash memory package can achieve dramatically high performance and low power consumption comparing with any conventional NAND-type flash memory. Our results show that the NAND flash memory package with a smart buffer cache can reduce the miss ratio by around 70% and the average memory access time by around 67%, over the conventional NAND flash memory configuration. Also, the average miss ratio and average memory access time of the package module with smart buffer for a given buffer space (e.g., 3KB) can achieve better performance than package modules with a conventional direct-mapped buffer with eight times(e.g., 32KB) as much space and a fully-associative configuration with twice as much space(e.g., 8KB)

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.1003-1012
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• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

• The Journal of Society for e-Business Studies
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• v.14 no.1
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• pp.143-160
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• 2009

In determining the performance of OLAP database applications, the structure and the effective access methods to the underlying disk system is a significant factor. In recent years, hard disks are designed with multiple physical zones where seek times and data transfer rates vary across the zones. However, there is little consideration of multi-zone disks in previous works. Instead, they assumed a traditional disk model that comes with many simplifying assumptions such as an average seek-time and a single data transfer rate. In this paper, we propose a technique storing a set of materialized views into the multi-zoned disks in OLAP environment dealing with large sets of data. We first present the disk zoning algorithm of materialized views according to the access probabilities of each views. Also, we address the problem of storing views in the dynamic environment where data are updated continuously. Finally, through experiments, we prove the performance improvement of the proposed algorithm against the conventional methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.48-58
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• 2002

As internet traffic increases, the problem that it should be efficiently accepted in to the existing voice network in the pending problem importantly to the existing communication corporations. The feature of next generation exchange network is made up of the form of integration network that connect data traffic(internet service. Etc) with the existing voice network and it can be showed with very diverse aspects according to the constitution time of network or the characteristics of business. The progress strategy that develop the existing circuit based communication network into packet-based communication network can be divided into two in a large scale according to the application position These are VoDSL application method(Technology that packetize access network) and softswitch technology application method(after packetizing relay network, packetizing that into the access network). In this paper, we will deduce the desirable technology that can construct packet-based next generation exchange networks in the structure of the existing communication network environment. We will perform the research on a device to offer the necessary core technique VoSDL service with realistic resolutions primarily.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.85-94
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• 2004

In this paper, a register allocation techlique that translates memory accesses to register accesses Is presented to enhance embedded software performance. In the proposed method, a source code is profiled to generate a memory trace. From the profiling results, target functions with high dynamic call counts are selected, and the proposed register allocation technique is applied only to the target functions to save the compilation time. The memory trace of the target functions is searched for the memory accesses that result in cycle count reduction when replaced by register accesses, and they are translated to register accesses by modifying the intermediate code and allocating Promotion registers. The experiments where the performance is measured in terms of the cycle count on MediaBench and DSPstone benchmark programs show that the proposed method increases the performance by 14% and 18% on the average for ARM and MCORE, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1589-1598
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• 2014

To support the WBAN, IEEE 802.15 Task Group 6 announced standardized documents on technical requirements of the PHY and MAC. In the IEEE 802.15.6 MAC protocol, CSMA/CA(Carrier Sense Multiple Access with Collision Avoidance) algorithm is performed based on the eight-level priorities according to the type of traffics of the periodic data from medical sensor nodes. Several nodes, which detected the changed bio signals, transmit emergency data at the same time, so latency could be higher than emergency latency and energy consumption will increase. In this thesis, we proposed a CSMA/CA algorithm in WBAN to solve these problems. Simulations are performed using a Castalia based on the OMNeT++ network simulation framework to estimate the performance of the proposed superframe and algorithms. Performance evaluation results show that the packet transmission success rate and energy efficiency are improved by reducing the probability of collision using the proposed MAC protocol.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

• Journal of Korea Game Society
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• v.13 no.2
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• pp.39-48
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• 2013

In MMORPGs(Massively Multi-player Online Role-Playing Games) a large number of players actively interact with one another in a virtual world. Therefore MMORGs must be able to quickly process real-time access requests and process requests from numerous gaming users. A key challenge is that the workload of the game server increases as the number of gaming users increases. To address this workload problem, many developers apply with distributed server architectures which use dynamic map partitioning and load balancing according to the server function. Therefore most MMORPG servers partition a virtual world into zones and each zone runs on multiple game servers. These methods cause of players frequently move between game servers, which imposes high overhead for data updates. In this paper, we propose a new architecture that apply with an arithmetic server dedicated to data operation. This architecture enables the existing game servers to process more access and job requests by reducing the load. Through mathematical modeling and experimental results, we show that our scheme yields higher efficiency than the existing ones.