• Proceedings of the Korean Information Science Society Conference
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• 2004.10c
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• pp.709-711
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• 2004

네트워크에서의 IP address는 통신을 하기 위한 가장 중요한 요소라고 할 수 있다. 네트워크 상에 존재하는 모든 node들은 자신의 IP address를 가지고 나서야 통신에 참여할 수 있다. 최근 MANET에서의 라우팅 프로토콜에 대한 많은 연구가 진행되고 있으며, 이와 함께 dynamic addressing technique에 대한 연구도 활발히 이루어지고 있다. 본 논문에서는 여러 가지 방식의 dynamic addressing technique들 중에서 빠르고 효율적인 Dynamic Configuration and Distribution Protocol (DCDP)에 대해 살펴보고 보다 안정적인 address 할당 기술을 이용한 Enhanced DCDP를 제안한다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.2
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• pp.731-763
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• 2017

In Underwater Linear Sensor Networks (UW-LSN) routing process, nodes without proper address make it difficult to determine relative sensor details specially the position of the node. In addition, it effects to determine the exact leakage position with minimized delay for long range underwater pipeline monitoring. Several studies have been made to overcome the mentioned issues. However, little attention has been given to minimize communication delay using dynamic addressing schemes. This paper presents the novel solution called Hop-by-Hop Dynamic Addressing based Routing Protocol for Pipeline Monitoring (H2-DARP-PM) to deal with nodes addressing and communication delay. H2-DARP-PM assigns a dynamic hop address to every participating node in an efficient manner. Dynamic addressing mechanism employed by H2-DARP-PM differentiates the heterogeneous types of sensor nodes thereby helping to control the traffic flows between the nodes. The proposed dynamic addressing mechanism provides support in the selection of an appropriate next hop neighbour. Simulation results and analytical model illustrate that H2-DARP-PM addressing support distribution of topology into different ranges of heterogeneous sensors and sinks to mitigate the higher delay issue. One of the distinguishing characteristics of H2-DARP-PM has the capability to operate with a fewer number of sensor nodes deployed for long-range underwater pipeline monitoring.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.764-767
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• 2003

We have experimentally investigated the influence of wall charge configurations prior to addressing discharge on dynamic margin in AC plasma display panel. In this experiment, we have analyzed the quantity and polarity of wall charge accumulated on the front and rear dielectrics just prior to the addressing discharge under the conventional driving sequence.

• Journal of Communications and Networks
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• v.8 no.4
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• pp.378-390
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• 2006

Many distributed applications build overlays on top of the Internet. Several unsolved issues at the network layer can explain this trend to implement network services such as multicast, mobility, and security at the application layer. On one hand, overlays creating basic topologies are usually limited in flexibility and scalability. On the other hand, overlays creating complex topologies require some form of application level addressing, routing, and naming mechanisms. Our aim is to design an efficient and robust addressing, routing, and naming infrastructure for these complex overlays. Our only assumption is that they are deployed over the Internet topology. Applications that use our middleware will be relieved from managing their own overlay topologies. Our infrastructure is based on the separation of the naming and the addressing planes and provides a convergence plane for the current heterogeneous Internet environment. To implement this property, we have designed a scalable distributed k-resilient name to address binding system. This paper describes the design of our overlay infrastructure and presents performance results concerning its routing scalability, its path inflation efficiency and its resilience to network dynamics.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.83-86
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• 2009

BiNem$^{(R)}$ displays have entered volume manufacturing in 2009. Applications range from e-labels to e-readers. We have developed 6-inch $960{\times}720$ pixels passive matrix BiNem prototypes achieving 40 % brightness and fluid user interface based on partial image / dynamic pointer addressing. Active-matrix addressing is proposed to provide even faster operation.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.564-567
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• 2004

New address electrode having separated dual electrode is suggested to reduce addressing time in ac PDP. Addressing characteristics of suggested electrode has been investigated in the test panel with high Xe partial pressure. It has been found that both the formative and jitter width of the suggested electrode is improved by 10 -20 % over the wide range of address voltage level compared with the conventional one. The dynamic margin of the panel also greatly improved. The key feature behind this type of structure is that it can extend the controllability of the wall charge distribution during the reset and address discharge without significant increase in capacitive load of address electrode.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.443-452
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• 2009

Although 32-bit architectures are becoming the norm for modern microprocessors, 16-bit ones are still employed by many low-end processors, for which small size and low power consumption are of high priority. However, 16-bit architectures have a critical disadvantage for embedded processors that they do not provide enough encoding space to add special instructions coined for certain applications. To overcome this, many existing architectures adopt non-orthogonal, irregular instruction sets to accommodate a variety of unusual addressing modes. In general, these non-orthogonal architectures are regarded compiler-unfriendly as they tend to requires extremely sophisticated compiler techniques for optimal code generation. To address this issue, we proposed a compiler-friendly processor with a new addressing mode, called the dynamic implied addressing mode(DIAM). In this paper, we will demonstrate that the DIAM provides more encoding space for our 16-bit processor so that we are able to support more instructions specially customized for our applications. And we will explain the advanced architecture which has improved performance. In our experiment, the proposed architecture shows 11.6% performance increase on average, as compared to the basic architecture.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.6
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• pp.568-572
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• 2009

We present a ternary microfluidic multiplexer unit, capable to address three flow channels using a pair of control lines with two different threshold pressure valves. The previous binary multiplexer unit addresses only two flow channels using a pair of control line with identical threshold pressure valves, thus addressing $2^{n/2}$ flow channels using n control lines. The present ternary multiplexer addressing three flow channels using a pair of control lines, however, is capable to address $3^{n/2}$ flow channels using n control lines with two different threshold pressure valves. In the experimental study, we characterized the threshold pressure and the response time of the valves used in the ternary multiplexer. From the experimental observation, we also verified that the present ternary multiplexer unit could be operated by two equivalent valve operating conditions: the different static pressures and dynamic pressures at different duty ratio. And then, $3{\times}3$ well array stacking ternary multiplexers in serial is addressed in cross and plus patterns, thus demonstrating the individual flow channel addressing capability of the ternary multiplexer. Thus, the present ternary multiplexer reduces the number of control lines for addressing flow channels, achieving the high well control efficiency required for simple and compact microfluidic systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.1-8
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• 2004

We developed a new PDP gray scale implementation method on the basis of the quantized memory addressing(QMA) principle. We defined three wall charge states; 'fully-on', 'off', and 'half-on', by controlling the width of address pulses. With these three wall charge state, we were able to express 255 level gray scale with only 7 sub-fields. Furthermore, in contrast to the conventional driving methods, the sub-field combinations for any two adjacent gray levels differ by only 1 sub-field, at worst, and therefore, eliminate the dynamic false contours. Since this method use 7 sub-field, the sustain discharge Period is increased by more than $70\%$ compared to the 12 sub-field method which reduces the dynamic false contours.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.647-650
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• 2005

A new driving scheme, Address and Display Period Complex Driving for Expanding Gray Scale(ACE), is proposed by mixing Address Display period Separated(ADS) and Address While Display(AWD). In this method scan lines are divided in blocks driving by AWD and scan lines in block progress sequential high speed addressing. ADS driving get accomplished in low gray level for expanding gray scale. Scan time is reduced and the number of subfields is increased by high speed addressing of ACE. That expands the gray scale and decreases the dynamic false contour. Also, that improves contrast by using ramp reset.