• Physical Therapy Korea
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• v.12 no.2
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• pp.90-97
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• 2005

By measuring changes in blood lactate and plasma enzyme (CPK, GOT, GPT) with electrical stimulation applied at two duty cycles, this study is intended to look into which type of duty cycle may have more effects on blood lactate and plasma enzyme constituents through animal experiment so as to determine any duty cycle appropriate for electrical treatment. In this study, electrical stimulation was applied to total 20 Korean house rabbits (weight: 3~3.5 kg) by means of an electrical therapeutic apparatus called TS6000 (made in Netherlands) at duty cycle of 50% and 20% respectively for 30 minutes. Here, 5 cc of blood was collected from their carotid artery before stimulation and in 30 minutes after stimulation respectively to carry out biochemical experiment and analysis. As determined through the above experiment, blood lactate rate was increased to 333.07% at 50% duty cycle after experiment and 185.71% at 20% duty cycle after experiment respectively. In both cases, blood lactate rate was significantly increased to higher level after electrical stimulation than before. Moreover, the rate of change in the average of blood lactate rate at both duty cycles also showed significant differences. CPK rate was boosted to 301.82% at 50% duty cycle after experiment and 321.35% at 20% duty cycle after experiment respectively. In both cases, CPK rate was remarkably boosted to higher level after stimulation than before (p<.05). However, there was not any significant difference in the rate of change in average CPK at both duty cycles (p<.05). GOT rate was significantly boosted up to 38.97% at 50% duty cycle after experiment (p<.05), while it was slightly increased to 1.68% at 20% duty cycle after experiment without any significant difference. Rather, GPT rate dropped slightly at both duty cycles after experiment, but there was not any significant difference. Although blood lactate and GOT were relatively less generated at 20% duty cycle after electrical stimulation than at 50% duty cycle, the change of duty cycle didn't have any significant influence on CPK rate. In this regard, this study failed to come any consistent conclusion about the association between change of duty cycle and muscle fatigue. Therefore, it is advisable that follow-up studies seek various ways to a little more effectively apply electrical stimulation to laboratory animals by avoiding their muscle fatigue. GOT rate was significantly boosted up to 38.97% at 50% duty cycle after experiment (p<.05), while it was slightly increased to 1.68% at 20% duty cycle after experiment without any significant difference. Rather, GPT rate dropped slightly at both duty cycles after experiment, but there was not any significant difference. Although blood lactate and GOT were relatively less generated at 20% duty cycle after electrical stimulation than at 50% duty cycle, the change of duty cycle didn't have any significant influence on CPK rate. In this regard, this study failed to come any consistent conclusion about the association between change of duty cycle and muscle fatigue. Therefore, it is advisable that follow-up studies seek various ways to a little more effectively apply electrical stimulation to laboratory animals by avoiding their muscle fatigue.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.854-857
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• 2008

Wireless sensor consists of an internal power source which has limited life time. Several MAC protocols have exploited scheduled sleep/listen cycles to conserve energy in sensor networks. Duty cycle is a user-adjustable parameter in low duty cycle MAC protocols, which determines the length of the sleep period in a frame. The sire of duty cycle has direct effect on the Performance of MAC Protocols. In this Paper, we simulated TEEM (A Traffic Aware, Energy Efficient MAC) and S-MAC in NS-2 with different duty cycle values and analyze how duty-cycle effects on the performance and energy consumption of both the protocols.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.55 no.10
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• pp.399-409
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• 2006

This paper presents a novel method for satisfying the thermal comfort of indoor environment and reducing the summer peak demand power by minimizing the power consumption for an Air-conditioner within a space. Korea Electric Power Corporation (KEPCO) use the fixed duty cycle control method regardless of the indoor thermal environment. However, this method has disadvantages that energy saving depends on the set-point value of the Air-Conditioner and direct load control (DLC) has no net effects on Air-conditioners if the appliance has a lower operating cycle than the fixed duty cycle. In this paper, the variable duty cycle control method is proposed in order to compensate the weakness of conventional fixed duty cycle control method and improve the satisfaction of residents and the reduction of peak demand. The proposed method estimates the predict mean vote (PMV) at the next step with predicted temperature and humidity using the back propagation neural network model. It is possible to reduce the energy consumption by maintaining the Air-conditioner's OFF state when the PMV lies in the thermal comfort range. To verify the effectiveness of the proposed variable duty cycle control method, the case study is performed using the historical data on Sep. 7th, 2001 acquired at a classroom in Seoul and the obtained results are compared with the fixed duty cycle control method.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.51-58
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• 2013

A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-${\mu}m$ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.10
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• pp.691-699
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• 2014

In order to increase network lifetime, duty-cycle MAC protocols which can reduce energy consumption caused by idle listening is proposed for WSNs. In common duty-cycle MAC protocols, each sensor node calculates its duty-cycle interval based on the current amount of residual energy. However, in WSNs with the capability of energy harvesting, existing duty-cycle intervals based on the residual energy may cause the sensor nodes which have high energy harvesting rate to suffer unnecessary sleep latency. Therefore, a duty-cycle scheduling scheme which adjust the duty-cycle interval based on both of the residual energy and the energy harvesting rate was proposed in our previous work. However, since this duty-cycle MAC protocol overlooked the performance variation according to the change of duty-cycle interval and adjusted the duty-cycle interval only linearly, the optimal duty-cycle interval could not be obtained to meet application requirements. In this paper, we propose three methods which calculate the duty-cycle interval and analyse their results. Through simulation study, we verify that network lifetime, end-to-end delay and packet delivery ratio can be improved up to 23%, 44% and 31% as compared to the existing linear duty-cycle scheduling method, respectively.

• Journal of Power Electronics
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• v.13 no.5
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• pp.757-765
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• 2013

For conventional interleaved two-phase forward converters with a common output inductor, the maximum duty cycle is 0.5, which limits the voltage range and increases the difficulty of the transformer's optimization. A new two-phase hybrid forward converter with series-parallel auto-regulated transformer windings is presented in this paper. With interleaved control signals for the two phases, the secondary windings of the transformers can work in series when the duty cycle is larger than 0.5, and they can work in parallel when duty cycle is lower than 0.5. Therefore, the maximum duty cycle is extended and the turns ratio of the transformer can be optimized. Duty cycle dependent auto-regulated windings result in the steady states of the converter being different in different duty cycle ranges (D>0.5 and D<0.5). Fortunately, the steady state gains of the proposed hybrid converter are identical at different duty cycle ranges, which means a stepless shift between two states. A prototype is built to verify the theoretical analysis. A conventional control loop is compatible for the whole input voltage range and load range thanks to the stepless shifting between the different duty cycle ranges.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.4
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• pp.1076-1089
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• 2012

Home automation networks are good environments for merging sensor networks and consumer electronics technologies. It is very important to reduce the energy consumption of each sensor node because sensor nodes operate with limited power based on a battery that cannot be easily replaced. One of the primary mechanisms for achieving low energy operation in energy-constrained wireless sensor networks is the duty-cycle operation, but this operation has several problems. For example, unnecessary energy consumption occurs during synchronization between transmission schedules and sleep schedules. In addition, a low duty-cycle usually causes more performance degradation, if the network becomes congested. Therefore, an appropriate control scheme is required to solve these problems. In this paper, we propose UDC (Unsynchronized Duty-cycle Control), which prevents energy waste caused by unnecessary preamble transmission and avoids congestion using duty-cycle adjustment. In addition, the scheme adjusts the starting point of the duty-cycle in order to reduce sleep delay. Our simulation results show that UDC improves the reliability and energy efficiency while reducing the end-to-end delay of the unsynchronized duty-cycled MAC (Media Access Control) protocol in sensor-based home automation networks.

• International journal of advanced smart convergence
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• v.7 no.4
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• pp.19-26
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• 2018

One of the distinct features of Wireless Sensor Networks (WSNs) is duty cycling mechanism, which is used to conserve energy and extend the network lifetime. Large duty cycle interval introduces lower energy consumption, meanwhile longer end-to-end (E2E) delay. In this paper, we introduce an energy consumption minimization problem for duty-cycled WSNs. We have applied Q-learning algorithm to obtain the maximum duty cycle interval which supports various delay requirements and given Delay Success ratio (DSR) i.e. the required probability of packets arriving at the sink before given delay bound. Our approach only requires sink to compute Q-leaning which makes it practical to implement. Nodes in the different group have the different duty cycle interval in our proposed method and nodes don't need to know the information of the neighboring node. Performance metrics show that our proposed scheme outperforms existing algorithms in terms of energy efficiency while assuring the required delay bound and DSR.