• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.532-542
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• 2009

Dynamic Thermal Management (DTM) technique is generally used for reducing the peak temperature (hotspot) in the microprocessors. Despite the advantages of lower cooling cost and improved stability, the DTM technique inevitably suffers from performance loss. This paper proposes the DualFloating-Point Adders Architecture to minimize the performance loss due to thermal problem when the floating-point applications are executed. During running floating-point applications, only one of two floating-point adders is used selectively in the proposed architecture, leading to reduced peak temperature in the processor. We also propose a new floorplan technique, which creates Space for Heat Transfer Delay in the processor for solving the thermal problem due to heat transfer between adjacent hot units. As a result, the peak temperature drops by $5.3^{\circ}C$ on the average (maximum $10.8^{\circ}C$ for the processor where the DTM is adopted, consequently giving a solution to the thermal problem. Moreover, the processor performance is improved by 41% on the average by reducing the stall time due to the DTM.

• The Journal of the Korea Contents Association
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• v.6 no.1
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• pp.8-13
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• 2006

In this thesis, an automatic door lock system using a dual tone multiple frequency(DTMF) signal generated as pushing the key button of mobile phone is proposed and implemented. This system consists of a transmitter module and a receiver module for processing the DTMF signal of mobile phone. The DTMF signal of mobile phone connected with ear-phone jack enter into the input terminal of DTMF receiver and those are encoded by a code-converter with 4-bits binary format in the DTMF receiver. The encoded output signals are transmitted to the amplitude shift keying(ASK) modulator of transmitter module and the modulated ASK signals which are converted into radio frequency(RF) signals propagate in a free space. The RF signals passed through a free space are demodulated by the ASK demodulator of receiver module and the demodulated ASK signals are sent to a micro-controller unit(MCU). The output signals processed by the MCU are compared with the secreted identification number which is prerecorded in a microprocessor and are transferred to a power relay. If the result is the same, the automatic door lock system opens a door. In the opposite case, it maintains closing the door. The implemented automatic door lock system operates well in mobile environments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1166-1174
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• 2004

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.49-56
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• 2004

The performance of the multiprocessor systems is limited by the several factors. The system performance is affected by the processor speed, memory delay, and interconnection network bandwidth/latency. By the evolution of semiconductor technology, off the shelf microprocessor speed breaks beyond GHz, and the processors can be scalable up to multiprocessor system by connecting through the interconnection networks. In this situation, the system performances are bound by the latencies and the bandwidth of the interconnection networks. SCI, Myrinet, and Gigabit Ethernet are widely adopted as a high-speed interconnection network links for the high performance cluster systems. Performance improvement of the interconnection network can be achieved by the bandwidth extension and the latency minimization. Speed up of the operation clock speed is a simple way to accomplish the bandwidth and latency betterment, while its physical distance makes the difficulties to attain the high frequency clock. Hence the system performance and scalability suffered from the interconnection network limitation. Duplicating the link of the interconnection network is one of the solutions to resolve the bottleneck of the scalable systems. Dual-ring SCI link structure is an example of the interconnection network improvement. In this paper, I propose a network topology and a transaction path algorism, which optimize the latency and the efficiency under the duplicated links. By the simulation results, the proposed structure shows 1.05 to 1.11 times better latency, and exhibits 1.42 to 2.1 times faster execution compared to the dual ring systems.

• Korean Journal of Optics and Photonics
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• v.4 no.1
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• pp.15-21
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• 1993

This paper describes the design and development of a KrF excimer laser stepper and discusses the detailed system parameters and characterization data obtained from the performance test. We have developed a deep UV step-and-repeat system, operating at 248 nm, by retrofitting a commercial modules such as KrF excimer laser, precision wafer stage and fused silica illumination and 5X projection optics of numerical aperture 0.42. What we have developed, to the basic structure, are wafer alignment optics, reticle alignment system, autofocusing/leveling mechanisms and environment chamber. Finally, all these subsystem were integrated under the control of microprocessor-based controllers and computer. The wafer alignment system comprises the OFF-AXIS and the TTL alignment. The OFF-AXIS alignment system was realized with two kinds of optics. One is the magnification system with the image processing technique and the other is He-Ne laser diffraction type system using the alignment grating on the wafer. 'The TTL alignment system employs a dual beam inteferometric method, which takes advantages of higher diffraction efficiency compared with other TTL type alignment systems. As the results, alignment accuracy for OFF-AXIS and TTL alignment system were obtained within 0.1 $\mu\textrm{m}$/ 3 $\sigma$ for the various substrate on the wafers. The wafer focusing and leveling system is modified version of the conventional systems using position sensitive detectors (PSD). This type of detection method showed focusing and leveling accuracies of about $\pm$ 0.1 $\mu\textrm{m}$ and $\pm$ 0.5 arcsec, respectively. From the CD measurement, we obtained 0.4 $\mu\textrm{m}$ resolution features over the full field with routine use, and 0.3 $\mu\textrm{m}$ resolution was attainable under more strict conditions.