• Journal of IKEEE
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• v.17 no.4
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• pp.564-569
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• 2013

The current embedded devices are growing rapidly in the multi-core, and these demand fast boot time. But method of previous boot uses core only one. The method includes parallel techniques and modification of CPU Frequency policy. Parallel methods, after analyzing the Android boot process with analysis tool, applied to location where a lot of CPU operation. CPU Frequency policy is modified for high performance of core. The proposed method was applied to S5PV310 dual core and Exynos4412 quad core embedded system. As a result of the experiment, we found that the proposed method makes boot time fast about 20.71% and 31.34% in dual core and quad core environment as compared with the previous method.

• Steel and Composite Structures
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• v.44 no.1
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• pp.105-117
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• 2022

Impact resistance efficiency of the newly designed sandwich beam with a laterally arched core as bio-inspired by the woodpecker is numerically investigated. The principal components of the beam comprise a dual-core system sandwiched by the top and bottom laminated CFRP skins. Different materials, including hot melt adhesive, high-density polyethylene (HDPE), acrylonitrile butadiene styrene (ABS), epoxy resin (EPON862), aluminum (Al6061), and mild carbon steel (AISI1018), are considered for the side-arched core layer of the beam for impact efficiency assessment. The aluminum honeycomb takes the role of the second core. Contact force, stress, damage formation, and impact energy for beams equipped with different materials are examined. A diversity in performance superiority is noticed in each of these indicators for different core materials. Therefore, for overall performance appraisal, the impact resistance efficiency index, which covers several chief impact performance parameters, of each sandwich beam is computed and compared. The impact resistance efficiency index of the structure equipped with the AISI1018 core is found to be the highest, about 3-10 times greater than other specimens, thus demonstrating its efficacy as the optimal material for the bio-inspired dual-core sandwich beam system.

• ETRI Journal
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• v.37 no.6
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• pp.1143-1153
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• 2015

In this paper, we propose an efficient architecture for a real-time image stitching engine for vision SoCs found in motor vehicles. To enlarge the obstacle-detection distance and area for safety, we adopt panoramic images from multiple telegraphic cameras. We propose a stitching method based on a fixed homography that is educed from the initial frame of a video sequence and is used to warp all input images without regeneration. Because the fixed homography is generated only once at the initial state, we can calculate it using SW to reduce HW costs. The proposed warping HW engine is based on a linear transform of the pixel positions of warped images and can reduce the computational complexity by 90% or more as compared to a conventional method. A dual-core SW/HW image stitching engine is applied to stitching input frames in parallel to improve the performance by 70% or more as compared to a single-core engine operation. In addition, a dual-core structure is used to detect a failure in state machines using rock-step logic to satisfy the ISO26262 standard. The dual-core SW/HW image stitching engine is fabricated in SoC with 254,968 gate counts using Global Foundry's 65 nm CMOS process. The single-core engine can make panoramic images from three YCbCr 4:2:0 formatted VGA images at 44 frames per second and frequency of 200 MHz without an LCD display.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.6
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• pp.703-709
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• 2014

In the AMP(Asymmetric Multiprocessing) based dual core using core-specific operating system in a single processor system, shared memory method is used to send data between processors in dual core. To used shared memory in different operating systems, there is a problem of needing to solving the issue of message communication and synchronization between the two operations systems. In this paper, separate memory controller was used for data sharing between different processor cores in dual core environment. This controller can designate two slave ports to allow simultaneous access from two processors, and in the case of process data simultaneously by two processors, priority order of slave ports is determined through memory mediator. When sending data from A to B processor, SRAM area was logically separated into 8 pages. It allowed using memory area from multiple processes with the size of 4KByte per page, and control register with the size of 4Byte was used to discern the usability of current page.

• Journal of Internet Computing and Services
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• v.11 no.4
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• pp.95-106
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• 2010

Recently multiple process communicate together. They share resource and information for cooperation in complicated programming environment. Kernel provides IPC (Inter -Process Communication) for communication with each other process. Shared Memory is a technique that many processes can access to identical memory area in the Linux environment. In this paper, we propose a performance improvement method of shared memory in the dual-core embedded linux system which is consist of different core and different operating system. We construct the MPC2530F (ARM926F+ARM946E) linux system and measure the performance therein. We attempt a performance enhancement in each CPU for each process which uses a shared memory.

• Kyungpook Mathematical Journal
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• v.55 no.2
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• pp.355-372
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• 2015

In the present paper, by using the Fibonacci difference matrix, we introduce the almost convergent sequence space $\hat{c}^f$. Also, we show that the spaces $\hat{c}^f$and $\hat{c}$ are linearly isomorphic. Further, we determine the ${\beta}$-dual of the space $\hat{c}^f$ and characterize some matrix classses on this space. Finally, Fibonacci core of a complex-valued sequence has been introduced, and we prove some inclusion theorems related to this new type of core.

• Journal of Dental Rehabilitation and Applied Science
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• v.23 no.4
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• pp.283-292
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• 2007

Two-step or one-step bonding systems generally inhibit curing process of dual-cured core build-up resin composite for their adhesive acidity. In addition this dual-cured core build-up resin composite can be applied to dentin of pulp chamber and root at the time that complete the endodontic treatment. The purpose of this investigation was to determine the influence of sodium hypochlorite on rnicrotensile bond strength of dual-cured core build-up resin composite. Extracted human molars were horizontally sectioned with 1mm thickness using low speed diamond saw. After the sectioned specimens were divided into 8 groups, adhesive systems (Clearfil SE-Bond, Prime&Bond NT[2-step, 1-step], Adper Prompt L-Pop) were then applied with or without sodium hypochlorite pretreatment. The treated specimen was filled with dual-cured core build-up resin composite (Luxacore, DMG corp., German). Then light cured for 40 seconds and soaked in $37^{\circ}C$ water bath for 24 hours. After the treated specimen was grinded with 1mm width and measured rnicrotensile bond strength by testing machine. Additionally 8 teeth were prepared for SEM evaluation. The results were as follows. : NaOCl treated groups generally had lower rnicrotensile bond strength but did not show any difference statistically except Adper Prompt L-Pop. When the teeth were treated by NaOCl, though the difference of applied adhesive system, it had no statistically significant difference within the NaOCl treated groups except the relation of between ClearFil SE-Bond adhesive system and Adper Prompt L-Pop adhesive system. In the SEM evaluation, NaOCl treated groups presented relatively long resin tags and incomplete hybrid layer formation generally.

• Journal of electromagnetic engineering and science
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• v.10 no.4
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• pp.309-315
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• 2010

A dual-band dual-polarized microstrip antenna array for an advanced multi-function radio function concept (AMRFC) radar application operating at S and X-bands is proposed. Two stacked planar arrays with three different thin substrates (RT/Duroid 5880 substrates with $\varepsilon_r$=2.2 and three different thicknesses of 0.253 mm, 0.508 mm and 0.762 mm) are integrated to provide simultaneous operation at S band (3~3.3 GHz) and X band (9~11 GHz). To allow similar scan ranges for both bands, the S-band elements are selected as perforated patches to enable the placement of the X-band elements within them. Square patches are used as the radiating elements for the X-band. Good agreement exists between the simulated and the measured results. The measured impedance bandwidth (VSWR$\leq$2) of the prototype array reaches 9.5 % and 25 % for the S- and X-bands, respectively. The measured isolation between the two orthogonal polarizations for both bands is better than 15 dB. The measured cross-polarization level is ${\leq}-21$ dB for the S-band and ${\leq}-20$ dB for the X-band.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.95-100
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• 2022

In this paper, a power loss analysis technique of a high-frequency transformer of a bidirectional DAB (Dual Active Bridge) converter is reported. To miniaturize the transformer of the dual active bridge converter, a resonant inductor was designed with an air gap included low-coupled rate state core to combine leakage inductor with the resonant inductor which is required for soft-switching. In this paper, leakage inductance and magnetizing inductance, core material, type of winding and winding method are included in the dual active bridge transformer loss analysis process to enable optimal design at the initial design stage. Transformer loss analysis for dual active bridge with a switching frequency of 200 kHz and maximum output of 5 kW was executed, and elements necessary for design based on the number of turns on the primary side were graphed while maintaining the transformer turns ratio and window area. In particular, it was possible to determine the optimal number of turns and thickness of the transformer, and ultimately, the total loss of the transformer could be estimated.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.15-20
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• 2002

In this project, we hale developed various techniques for subminiaturization, surface implementation, high frequency design, small-size SMD, performance test and application of the Dual PLL module, which is a core component for the personal communication systems. We also obtained base techniques for the next-generation Dual PLL module design and fabrication techniques for an internationally competitive subminiature Dual PLL module.