• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.7
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• pp.4918-4924
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• 2015

In this paper, we consider the capacity improvement of systems exploiting dual-polarized antennas for two-user transmission. To this end, we analyze the upper bounds of ergodic capacities for multicast and unicast data services in the systems, and propose the condition for adjusting the complex cross-polarization discriminations (XPDs) to maximize the ergodic capacities. In addition, we present the adjustment condition of the complex XPDs that can achieve spectral efficiencies close to the maximum ergodic capacities with lower system complexity. Lastly simulation results demonstrate that the systems using the proposed conditions can obtain higher spectral efficiencies than the ones employing different adjustment conditions including the exiting adjustment condition.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.6 s.109
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• pp.511-518
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• 2006

In this paper, a small RFID tag antenna in UHF band which has bandwidth-enhanced characteristic is proposed. The shape of the proposed antenna is a meander antenna to have size-reduced characteristic, and it consists of two radiators which make dual resonance in adjacent frequency to enhance bandwidth. By adjusting length and location of each radiator, the proposed antenna can make dual resonance at arbitrary location on the Smith chart, which is able to make impedance matching with RFID tag chip in wide frequency range. And it is apparent that the proposed antenna can have bandwidth-enhanced characteristic according to the simulated and measured results.

• The Journal of Korea Robotics Society
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• v.15 no.2
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• pp.100-106
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• 2020

In the agricultural field, interests in research using robots for fruit harvesting are continuously increasing. Dual arm manipulators are promising because of its abilities like task-distribution and role-sharing. To operate it efficiently, the task sequence must be planned adequately. In our previous study, a collision-free path planning method based on a genetic algorithm is proposed for dual arm manipulators doing tasks cooperatively. However, in order to simplify the complicated collision-check problem, the movement between tasks of two robots should be synchronized, and thus there is a problem that the robots must wait and resume their movement. In this paper, we propose a heuristic algorithm that can reduce the total time of the optimal solution obtained by using the previously proposed genetic algorithm. It iteratively desynchronizes the task sequence of two robots and reduces the waiting time. For evaluation, the proposed algorithm is applied to the same work as the previous study. As a result, we can obtain a faster solution having 22.57 s than that of the previous study having 24.081 s. It will be further studied to apply the proposed algorithm to the fruit harvesting.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.358-364
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• 2009

This paper shows some variable bias techniques which can improve the power added efficiency(PAE) for the designed power amplifier. Some simulations have been done to get the effect of the bias change, and variable bias is adopted to get the higher efficiency for dual mode amplifier which generates two different output power levels. With drain bias change and a fixed gate bias, the amplifier shows PAE improvement compared to the fixed bias amplifier. In addition, this paper analyzed nonlinear distortion of the power amplifier and has used the digital predistortion which can result in 10dB ACPR improvement for the dual band amplifier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.384-389
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• 2003

A new two-step soft-output Viterbi algorithm (SOVA) decoder architecture is presented. A significant reduction in the decoding latency can be achieved through the use of the dual-port RAM in the survivor memory structure of the trace-back unit. The system complexity can be lowered due to the determination of the absolute value of the path metric differences inside the add-compare-select (ACS) unit. The proposed SOVA architecture was verified successfully by the functional simulation of Verilog HDL modeling and the FPGA prototyping. The SOVA decoder achieves a data rate very close to that of the conventional Viterbi Algorithm (VA) decoder and the resource consumption of the realized SOVA decoder is only one and a half times larger than that of the conventional VA decoder.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.2
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• pp.184-191
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• 2013

In this paper, bidirectional AC-DC converter using dual half-bridge converter is proposed. A transformer leakage inductance in the dual half-bridge converter is used for making resonance with the capacitor of the voltage-doubler, which can help the switched current to be sinusoidal without extra inductive component and also the switching loss can be reduced through operation such as ZVS, ZCS. Both circuit analysis and design guideline are described, and also the feasibility for the proposed converter is shown through the hardware implementation and the experimental results.

• Proceedings of the KOSOMBE Conference
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• v.1997 no.11
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• pp.294-298
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• 1997

In the magnetic resonance imaging, the fast spin echo imaging technique is a widely used clinical imaging method, since its scanning time is much shorter than the conventional spin echo imaging and it gives the almost same image quality. However, the fast spin echo technique has two times longer imaging time or the dual echo acquisition which can obtain a spin density image and a $T_2$-weighted image simultaneously. To overcome such a drawback, this paper proposes a new fast dual echo imaging technique which can give the same quality images at the single echo imaging time. The proposed technique reduces the imaging time by overlapping most of echo train data for each image reconstruction. In order to verify its validity and usability the human head experimental results which were obtained at the 0.3T permanent MRI system are presented.

• Journal of the Korean Home Economics Association
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• v.36 no.10
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• pp.35-48
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• 1998

The Korean family is changing. The growth in dual-earner households has been the 'revolution' of the century, implying inevitable modification of the role division in marriage toward greater symmetry of responsibility for breadwinning and homemaking. So, the purpose of this study is to understand husbands' housework and to investigate the change of the husbands' housework. This means to investigate how the husband is related to housework. For these research purpose, 60 dual-earner couples were deeply interviewed. The major discussions of this study can be summarized as follows: There are four types of housework in men's work, the type of refusal, the type of avoidance, the type of inevitability, and the type of participation. These types are taken order to understand change in housework is women's work. Men in the type of avoidance in household work is 25%, they have a tendency to avoid housework with making any excuses. People in the type of inevitability is 20%. These men are compelled to work in household owing to circumstances beyond control. 13% of couples is type of participation. These have a new idea of housework. They don't get the gender role division. They can become a good husband. and eventually solve conflicts and problems in couples.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.23-29
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• 2004

In this paper, the asynchronous quasi dual-port SRAM employing a single port structure in SRAM embedded SOC (System On Chip) is proposed. External host can access the internal SRAM freely and the data on internal SRAM can be transferred to an another external circuitry without a synchronous signal of an external host, which operates as an asynchronous dual-port SRRAH The performances of the proposed circuits and control structure are verified through the simulation and we fabricated it using a 0.35um CMOS technology. As the results, the chip shows reduced area about 20% and saved power also 20% than conventional architectures.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.1-5
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• 2008

Although we can make a sparse matrices for LDPC codes, the encoding complexity per a block increases quadratically by $n^2$. We propose modified PEG algorithm using PEG algorithm having a large girth by establishing edges or connections between symbol and check nodes in an edge-by-edge manner. M-PEG construct parity check matrices. So we propose parity check matrices H form a dual-diagonal matrices that can construct a more efficient decoder using a M-PEG(modified Progressive Edge Growth).