• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.23-32
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• 2011

A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 ${\mu}m$ 1P6M CMOS technology and occupies 1.17 $mm^2$ including pads. It dissipates only 1.1 ${\mu}W$ with 1 V supply voltage while operating at 100 kS/s.

• Journal of IKEEE
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• v.14 no.2
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• pp.69-75
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• 2010

A 3D graphics pipeline is largely divided into geometry stage and rendering stage. In this paper, we propose a method that accelerates a geometry processing in multi-core GP-GPU, using dual-phase structure. It can be improved by parallel data processing using SIMD of GP-GPU, dual-phase structure and memory prefetch. The proposed architecture improves approximately 19% of performance when it use all the features.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.279-282
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• 1999

Frequency divider selects the channel of the frequency synthesizer. General programmable divider has many flip-flops to realize all integer division value and stability problem by using dual modules prescaler. In this paper, a new architecture of programmable divider is proposed and designed to improve these problems. The proposed programmable divider has only thirteen flip-flops. The programmable divider is designed by 0.65${\mu}{\textrm}{m}$ CMOS technology and HSPICE. Operating frequency of the programmable divider is 200MHz with a 3V supply voltage.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1991.10a
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• pp.137-140
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• 1991

The TDX-10 Time Switch architecture has modularity, high reliability and considerable large switch fabric having separated and both-way 1K time slot interchange switching circuit elements. In this paper, we present key functions, architecture, features and traffic characteristic of TDX-10 Time Switch. And we also describe some basic implementation technologies such as Frame Base Read-Write Separation Method, Multi-Write Method and Read-Write Separation Technique with Dual-port Memory.

• Korean Institute of Interior Design Journal
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• v.14 no.1
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• pp.3-10
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• 2005

The purpose of this study is to find the relationship between hightech architecture and digital one through the discussion on Karl B tticher's view on tectonic in 19th century. The discussion of tectonics which has not been brought up until recently. Since there are no studies regarding contemporary architecture relating to Karl B tticher's view on tectonic, so it is fairly significant to study Karl B tticher's conception, discussion and relationship of contemporary architecture. To study the essence and meaning of Karl B tticher's view on tectonic in 19th century, we will analyze each examples of hightech architecture and digital architecture through Karl B tticher's dual form. B tticher insist that dualistic relationship is united and produced simultaneously. Because they have so closed relationship each other, it's impossible to apply only decoration without structure. Therefore they have mutual assistant relationship. A relationship can be found between hightech architecture's technology and structural symbol that Karl B tticher tried to find in steel which is new material ornament. Digital architecture can be confirmed as images which are made of maximum expose through consistent dynamics of structure. Karl Btticher try to find structural symbolism between new meterail, iron, and decoration. In modern architecture it has the closed relationship with high-tech technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.11-23
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• 1995

In this paper, a parallel pipelined processor model which acts as a small VLIW processor architecture and a scheduling algorithm for extracting instruction-level parallelism on this architecture are proposed. The proposed model has a dual-instruction mode which has maximum 4 basic operations being executed in parallel. By combining these basic operations, variable instruction set can be designed for various applications. The scheduling algorithm schedules basic operations for parallel execution and removes pipeline hazards by examining data dependency and resource conflict relations. In order to examine operation and evaluate the performance,a C compiler and a simulator are developed. By simulating various test programs with the compiler and the simulator, the characteristics and the performance result of the proposed architecture are measured.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• International Journal of Naval Architecture and Ocean Engineering
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• v.8 no.4
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• pp.330-343
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• 2016

This paper presents results of an experimental investigation of vortex-induced vibration (VIV) of a flexibly mounted and rigid cylinder with two-degrees-of-freedom with respect to varying ratio of in-line natural frequency to cross-flow natural frequency, $f^*$, at a fixed low mass ratio. Combined in-line and cross-flow motion was observed in a sub-critical Reynolds number range. Three-dimensional displacement meter and tension meter were used to measure dynamic responses of the model. To validate the results and the experiment system, x and y response amplitudes and ratio of oscillation frequency to cross-flow natural frequency were compared with other experimental results. It has been found that the higher harmonics, such as third and more vibration components, can occur on a certain part of steel catenary riser under a condition of dual resonance mode. In the present work, however, due to the limitation of a size of circulating water channel, the whole test of a whole configuration of the riser at an adequate scale for VIV phenomenon was not able to be conducted. Instead, we have modeled a rigid cylinder and assumed that the cylinder is a part of steel catenary riser where the higher harmonic motions could occur. Through the experiment, we have found that even though the cylinder was assumed to be rigid, the occurrence of the higher harmonic motions was observed in a small reduced velocity ($V_r$) range, where the influence of the in-line response is relatively large. The transition of the vortex shedding mode from one to another was examined by using time history of x and y directional displacement over all experimental cases. We also observed the influence of in-line restoring force power spectral density with $f^*$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.