• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.458-466
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• 2012

A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.271-274
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• 1999

This paper proposes a simple architecture of digital dividing block in dual-modulus prescaler phase-locked loop used in the wireless communication. Proposed architecture eliminates a swallow counter in the conventional one and demonstrates the advantages in reducing the power consumption and the gate-counts. Therefore, it is suitable for small die area and low power applications. The circuit is designed in a standard 0.35${\mu}{\textrm}{m}$ CMOS process.

• Journal of Ship and Ocean Technology
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• v.6 no.2
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• pp.12-22
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• 2002

Offshore pipelines play an important role in the transportation of gas, oil, water and oil products. It is common to have a group of pipelines in the oil and gas field. To reduce the installation cost and time, dual pipelines are designed. There are great advantages in the installation of dual pipelines over two separate single lines. It can greatly reduce the cost for trench, back-filling and installation. However the installation of dual pipelines often requires technical challenges. Pipelines should be placed to be stable against external loadings during installation and design life period. Dual pipelines in trench can reduce the influence of external forces. To investigate the flow patterns and forces as trench depth and slope changes, number of experiments are conducted with PIV(Particle Image Velocimetry) equipment in a Circulating Water Channel. Numerical approaches to simulate experimental conditions are also made to compare with experimental results. The velocity fields around dual pipelines in trench are investigated and analysed. Comparison of both results show similar patterns of flow around pipelines. It is proved that the trench depth contributes significantly on hydrodynamic stability. The trench slope also affects the pipeline stability. The results can be applied in the stability design of dual pipelines in trench section. The complex flow patterns can be effectively linked in the understanding of fluid motions around multi-circular bodies in trench.

• Journal of Ocean Engineering and Technology
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• v.30 no.2
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• pp.125-133
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• 2016

In this paper, we propose a vertical axis water turbine with dual blades. A parametric study was conducted using numerical analyses. First, a two-dimensional finite-volume analysis with a commercial code was used to find the pitch angle of the main blade under different tip speed ratio conditions. Second, we developed a potential-based panel method to find the best configuration of the inner blades. Experimental tests were conducted at the circulating water channel of Chungnam National University. Various configurations of the dual blades were considered, and their performances were comparatively investigated. The results showed that the turbine with movable dual blades produces a constant torque and tip speed ratio at various flow rates.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.2
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• pp.105-115
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• 2002

Since NUMA architecture has to access remote memory an interconnection network determines the performance of CC-NUMA system Bus which has been used as a popular interconnection network has many limits to build a large-scale system because of the limited physical scalabilty and bandwidth Dual ring interconnection network composed of high speed point-to-point links is made up for resolving the defects of the bus for large-scale system But it also has a problem that the response latency is rapidly increased when many node are attached to snooping based CC-NUMA system with dual ring In this paper we propose a chordal ring architecture in order to overcome the problem of the dual ring on snooping based CC-NUMA system and design and efficient link controller adopted to this architecture. We also analyze the effects of chordal ring architecture on the system performance and the response latency by using probability driven simulator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.320-323
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• 2010

This paper proposes efficient log and exponent calculation methods using a dual phase instruction set without additional ALU unit for a mobile enviroment. Using the Dual Phase Instruction set, it extracts exponent and mantissa from expression of floating point and calculates 24bit single precision floating point of log approximation using the Taylor series expansion algorithm. And with dual phase instruction set, it reduces instruction excution cycles. The proposed Dual Phase architecture reduces the performance degradation and maintain smaller size.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.3
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• pp.107-114
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• 2005

In this paper. we propose an architecture of IEEE1394 device driver for RTLinux. The device driver has two interfaces for applications running on the RTLinux kernel and Linux kernel. With the interfaces, the device driver simultaneously supports RT-Thread of RTLinux kernel and user level process of Linux kernel. This architecture could be a reference for designing other device driver on the dual kernel platform.

• Journal of Welding and Joining
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• v.34 no.1
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• pp.41-46
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• 2016

With the recent increase in size of ships and offshore structures, there are more demand for thicker plates. As the thickness increases, it is known that fatigue life of the structures decrease. To improve the fatigue life, post weld treatments techniques, such as toe grinding, TIG dressing and hammer peening, are typically employed. However, these techniques require additional construction time and production cost. Therefore, it is of crucial interest steels with longer fatigue crack growth life compared to conventional steels. This study investigates fatigue crack growth rate (FCGR) behaviours of conventional EH36 steel and Ferrite-Bainite dual phase EH36 steel (F-B steel). F-B steel is known to have improved fatigue performance associated with the existence of two different phases. Ferrite-Bainite dual phase microstructures are obtained by special thermo mechanical control process (TMCP). FCGR behaviours are investigated by a series of constant stress-controlled FCGR tests. Considering all test conditions (ambient, low temperature, high stress ratio), it is shown that FCGR of F-B steel is slower than that of conventional EH36 steel. From the tensile tests and impact tests, F-B steel exhibits higher values of strength and impact energy leading to slower FCGR.

• Journal of Power Electronics
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• v.17 no.2
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• pp.398-410
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• 2017

This work presents the design of a dual extended Kalman filter (EKF) as a state/parameter estimator suitable for adaptive state-of-charge (SoC) estimation of an automotive lithium-iron-phosphate ($LiFePO_4$) cell. The design of both estimators is based on an experimentally identified, lumped-parameter equivalent battery electrical circuit model. In the proposed estimation scheme, the parameter estimator has been used to adapt the SoC EKF-based estimator, which may be sensitive to nonlinear map errors of battery parameters. A suitable weighting scheme has also been proposed to achieve a smooth transition between the parameter estimator-based adaptation and internal model within the SoC estimator. The effectiveness of the proposed SoC and parameter estimators, as well as the combined dual estimator, has been verified through computer simulations on the developed battery model subject to New European Driving Cycle (NEDC) related operating regimes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.515-520
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• 1998

In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.