• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.1
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• pp.97-102
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• 2016

In this paper, a bidirectional power supply charger is proposed. This system used a solar cell panel to generate electricity and used super capacitors to store these energies, which can be used for the robot cleaner or some other electronic products. This system include a phase-shift controlled bidirectional dual active bridge (DAB) converter, solar panel super capacitors and DSP controller. In the daytime it can charge to the super capacitors to store the energy generated by the solar cell panel and in the night it will release the energy stored in the super capacitors to loads. A prototype of the proposed bidirectional power supply charger system was designed which can achieve 18V to 30V input, 10V/20W output to super capacitors and 9V/6.5W output when it acts as a charger for the robot cleaner. The system is verified to be sTable and reliable by both the simulation and experimental results.

• Journal of the Korean Solar Energy Society
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• v.33 no.5
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• pp.69-75
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• 2013

To increase the efficiency of the photovoltaic, almost photovoltaic appliances are controlled by Maximum Power Point Tracking(MPPT). Existing most of the PV MPPT techniques have used power which multiplies sensed output current and voltage of the solar cell. However, these algorithms are unnecessarily complicated and too expensive for small and compact system. The other hand, the proposed MPPT technique is only one sensing of the MPPT converter's output current, so there is no need to insert another sensors of battery side. Therefore, this algorithm is simpler compared to the traditional approach and is suitable for low power solar system. Further, the novel proper charge/discharge algorithm for the battery with PV MPPT is developed. In this algorithm, there is CC battery charge mode and load discharge mode of the PV cell & battery dual. Also we design current control to regulate allowable current during the battery charging. The proposed algorithm will be applicable to battery included solar cell applications like solar lantern and solar remote control car. Finally, the proposed method has been verified with computer simulation.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.387-390
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• 2006

This paper presents a novel soft-switching PWM utility frequency AC to high frequency AC power conversion circuit Incorporating boost-half-bridge inverter topology, which is more suitable and acceptable for cost effective consumer induction heating applications. The operating principle and the operation modes are presented using the switching mode and the operating voltage and current waveforms. The performances of this high-frequency inverter using the latest IGBTs are illustrated, which includes high frequency power regulation and actual efficiency characteristics based on zero voltage soft switching (ZVS) operation ranges and the power dissipation as compared with those of the previously developed high-frequency inverter. In addition, a dual mode control scheme of this high frequency inverter based on asymmetrical pulse width modulation (PWM) and pulse density modulation (PDM) control scheme is discussed in this paper in order to extend the soft switching operation ranges and to improve the power conversion efficiency at the low power settings. The power converter practical effectiveness is substantially proved based on experimental results from practical design example.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.354-362
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• 2017

We investigated the improvement in electrical characteristics of large AlGaN/GaN on Si Schottky barrier diode (SBD) induced by structural change to achieve a better trade-off between the forward and reverse performance to obtain high power conversion efficiency in PFC converter. Using an optimized dry etch condition for a large device, we fabricated three-types of SBD with 63 mm channel width: conventional, recessed, recessed dual-anode-metal SBD. The recessed dual-anode-metal SBD exhibited a very low turn-on voltage of 0.34 V, a high forward current of 1.63 A at 1.5 V, a leakage current of $114{\mu}A$ at -15 V, a breakdown voltage of 794 V.

• Convergence Security Journal
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• v.3 no.1
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• pp.73-84
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• 2003

The IPv4 that used to be generally used as a medium of computer communications in 1980s has reached its limits now. IPv6 (IP Version 6) is being prepared to solve the limitations of the IPv4. However, the biggest problem of IPv6 is that it is not compatible with the IPv4. To resolve the compatibility issue, Dual Stack, Tunneling and Header Converting methods have been proposed. The Header Converting method allows communications between the IPv4 and IPv6 networks with the converter. This method's strength is that it is easy to embody and the procedures for embodiment is simple. However, this method still contains the weaknesses that the existing IPv4 has. On the current document, the Header Converting method among the three methods is discussed to resolve the problems this method has. To solve the Header Converting method's weakness, the security problem between sections, the IP Header field values are converted to the relative field values and IPSec (IP Security) and ESP (Encapsulation Security Payload) are applied. The proposed "Encrypted Header Converting Method" that is encrypted in packet units has solved the weakness that the pre-existing Header Converting method used to have.d to have.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.608-618
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• 2004

In this paper, modifying the diode star double balanced mixer of Maas, a novel resistive 60 GHz pHEMT MMIC star mixer is suggested. Due to star configuration, troublesome IF balun for ring configuration FET mixer is not necessary. In addition, the sysematic design method of dual balun through EM simulation is suggested rather than the design by inspection as Maas. The mixer circuit is fabricated as MMIC on CPW base using 0.1 um GaAs pHEMT Library of MINT in Dongguk University. The size is 1.5 ${\times}$ 1.5 $\textrm{mm}^2$ and its performance is adjustable by DC supply. It can be operated as both up and down converters and it shows the conversion loss of about 13∼18 ㏈ over the full V-band frequencies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.44-54
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• 2001

In this paper, a novel test method is proposed to detect the hard and soft fault in analog circuits. The proposed test method makes use of the offset voltage, which is one of the op-amps characteristics. During the test mode, CUT is modified to unit gain op-amps with feedback loop. When the input of the op-amp is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage. Faults in the op-amp which cause the offset voltage exceeding predefined range of tolerance can be detected. In the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time and cost is reduced. In this note, the validity of the proposed test method has been verified through the example of the dual slope A/D converter. The HSPICE simulations results affirm that the presented method assures a high fault coverage.

• Journal of Radiation Protection and Research
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• v.37 no.1
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• pp.16-24
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• 2012

In the present study, a gamma-ray detector and associated signal processing circuit was developed for a side-absorber of a dual-mode Compton camera. The gamma-ray detector was made by optically coupling a CsI(Tl) scintillation crystal to a silicon photodiode. The developed signal processing circuit consists of two parts, i.e., the slow part for energy measurement and the fast part for timing measurement. In the fast part, there are three components: (1) fast shaper, (2) leading-edge discriminator, and (3) TTL-to-NIM logic converter. AC coupling configuration between the detector and front-end electronics (FEE) was used. Because the noise properties of FEE can significantly affect the overall performance of the detection system, some design criteria were presented. The performance of the developed system was evaluated in terms of energy and timing resolutions. The evaluated energy resolution was 12.0% and 15.6% FWHM for 662 and 511 keV peaks, respectively. The evaluated timing resolution was 59.0 ns. In the conclusion, the methods to improve the performance were discussed because the developed gamma-ray detection system showed the performance that could be applicable but not satisfactory in Compton camera application.