• Title/Summary/Keyword: Dual Input

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A Study on the Development of Simulation Model for Inchon Port (인천내항을 위한 시뮬레이션 모델 개발)

  • 김동희;김봉선;이창호
    • Proceedings of the Safety Management and Science Conference
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    • 2000.05a
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    • pp.339-349
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    • 2000
  • Inchon Port is the second largest import-export port of Korea, and has the point at issue such as the excessive logistics cost because of the limits of handling capacity and the chronic demurrage. There are few research activities on the analysis and improvement of the whole port operation, because Inchon Port not only has the dual dock system and various facilities but also handles a various kind of cargo. The purpose of this paper is to develop the simulation program as a long-term strategic support tool, considering the dual dock system and the TU(Terminal Operation Company) system executed since March, 1997 in Inchon Port. The basic input parameters such as arrival intervals, cargo tons, service rates are analyzed and the probability density functions for these parameters are estimated. The main mechanism of simulation model is the discrete event-driven simulation and the next-event time advancing. The program is executed based on the knowledge base and database. From the simulation model, it is possible to estimate the demurrage status through analyzing various scenarios and to establish the long-term port strategic plan.

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A Dual-Mode Narrow-Band Channel Filter and Group-Delay Equalizer for a Ka-Band Satellite Transponder

  • Kahng, Sung-Tek;Uhm, Man-Seok;Lee, Seong-Pal
    • ETRI Journal
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    • v.25 no.5
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    • pp.379-386
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    • 2003
  • This paper presents the design of a narrow-band channel filter and its group-delay equalizer for a Ka-band satellite transponder. We used an 8th order channel filter for high selectivity with an elliptic-integral function response and an inline configuration. We designed a 2-pole, reflection-type, group-delay equalizer to compensate for the steep variation of the group-delay at the output of the channel filter, keeping the thermal stability at ${\pm}7$ ns of group-delay variation at the band edges over 15-55$^{\circ}C$. We devised a new tuning technique using short-ended dummy cavities and used it for tuning both the filter and equalizer; this removes the necessity of additional tuning after the cavities are assembled. Through measurement, we demonstrate that the group-delay-equalized filter meets the equipment requirements and is appropriate for satellite input multiplexers.

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Design of Dual-band Microstrip Antenna for ISM Bandwidth using Cross Patch (십자형 패치를 이용한 ISM 대역용 이중대역 마이크로스트립 안테나 설계)

  • 박기동;정문숙;임영석
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2002.11a
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    • pp.241-245
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    • 2002
  • Dual-band microstrip antenna is designed for industrial-scientific-medical(ISM) band of 2.4㎓ and 5.8㎓ using finite-difference time-domain method(FDTD). Cross Patch fed by aperture in the ground plane of microstrip line is proposed as radiation element of antenna, which is 2 rectangular Patch is overlapped. To design antenna, change of input impedance by aperture and stub length change is examined. And it is investigated that center frequency and -10 ㏈ bandwidth by Length of radiation element and width change. Experimental result about reflection Loss confirmed that agree well with analysis results of FDTD and IE3D, And -3 ㏈ beam width, front to back ratio and gain in frequency 2.43㎓ and 5.79㎓ is presented by measuring radiation Pattern of antenna.

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Real-Time fuzzy Control for Dual-Arm Robot Based-on TMS320C80 Chip (TMS320C80칩을 이용한 이중암 로봇의 실시간 퍼지제어)

  • 김홍래;김종수;한성현
    • Proceedings of the Korean Society of Machine Tool Engineers Conference
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    • 2003.04a
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    • pp.327-339
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    • 2003
  • In this paper, a self-organizing fuzzy controller(SOFC) for the industrial robot manipulator with a actuator located at the base is studied A fuzzy login composed of linguistic conditional statements is employed by defining the relations of input-output variable of the controller, In the synthesis of a FLC, one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult SOFC is proposed for a hierarchical control structure consisting of basic level and high level that modify control rules. The proposed SOFC scheme is simple in structure, fast in computations and suitable for implementation of real-time control. Performance of the SOFC is illustrated by simulation and experimental results for robot with low joints.

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Development of VLSI Process Simulator (반도체 공정 시뮬레이터 개발에 관한 연구)

  • 이경일;공성원;윤상호;이제희;원태영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1994.11a
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    • pp.40-45
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    • 1994
  • The TCAD(Technology Computer Aided Design) software tool is a popular name to be able to simulate the semiconductor process and device circuit. We have developed a two-dimensional TCAD software tool included an editor, parser, each process unit, and 2D, 3D graphic routine that is Integrated Environment. The initial grid for numerical analysis is automatically generated with the geometric series that use the user default(given) line and position separated with grid interval and the nodes corresponding to each mesh point stoic the all the possible attribute. Also, we made a data structure called PIF for input or output. Methods of ion implantation in this paper arc Monte Carlo, Gaussian Pearson and Dual-Pearson. Analytical model such as Gaussian, Pearson and Dual-Pearson were considered the multilayer structure and two-dimensional tilted implantation. We simuttaneously calculated the continuity equation of impurity and point defect in diffusion simulation. Oxidation process was simulated by analytical ERFC(Complementary Error Function) model for local oxidation.

Seismic Response of Haunch Repaired Steel MRFs: A Case Study (헌치로 보강된 철골모멘트 골조의 지진 응답: 사례연구)

  • 이철호
    • Proceedings of the Earthquake Engineering Society of Korea Conference
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    • 1997.04a
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    • pp.173-181
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    • 1997
  • To investigate the effects of haunch repair on the system seismic performance of steel moment-resisting frames (steel MRFs), a case study was conducted for a 13-story frame damaged during the 1994 Northridge earthquake. It was assumed that only those locations with reported damage would be repaired with haunches. A new analytical modeling technique for the dual panel zone developed by the author was incorporated in the analysis. Both the inelastic static and dynamic analyses did not indicate detrimental side effects resulting from the repair. As a result of the increased strength in dual panel zones, yielding in these locations were eliminated and larger plastic rotation demand occurred in the beams next to the shallow end of the haunches. Nevertheless, the beam plastic rotation demand produced by the Sylmar record of 1994 Northridge earthquake was still limited to 1.7% radians. The repair resulted in a minor increase in earthquake energy input. In the original structure, the panel zones should dissipate about 80%(for the Oxnard record) and 70%(for the Sylmar record) of the absorbed energy, assuming no brittle failure of moment connections. After repair, the energy dissipated in the panel zones and beams were about equal.

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Implementation of One-Cycle Control for Switched Capacitor Converters

  • Yang, Lei;Zhang, Xiaobin;Li, Guann-pyng
    • Journal of Power Electronics
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    • v.16 no.6
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    • pp.2057-2066
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    • 2016
  • An extension of the one-cycle control (OCC) method for switched-capacitor (SC) converters is proposed in this paper, featuring a fast dynamic response, wide line and load operation ranges, and simplicity in implementation. To illustrate the operation principle of this nonlinear control method and to demonstrate its simplicity in design, a dual-phase unity gain SC converter is examined. A new control loop based on the charge balance in a flying capacitor is formulated for the OCC technique and implemented with a 15W dual-phase unity gain SC converter on a circuit board for control verification. The obtained experimental results show that external disturbances can be rejected in one switching cycle by the OCC controlled SC converter with good line and load regulations. When compared to other control methods, the proposed nonlinear control loop exhibits superior dynamic performance in suppressing input and load disturbances.

A Dual-Band CMOS Low-Noise Amplifier

  • Oh, Tae-Hyoun;Jun, Hee-Suk;Jung, Yung-Ho;Shin, Hyung-Cheol
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.489-490
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    • 2006
  • This paper presents a switch type 2.4/5.8 GHz dual band low-noise amplifier, designed with $0.13{\mu}m$ RF CMOS technology. Using MOS switch allows the LNA to have two different input transconductance and output capacitance modes. Given supply voltage of 1.2 V, the simulation exhibits gains of 8.1 dB and 17.1 dB, noise figures of 3.1 dB and 2.57 dB and power consumptions of 13.0 mW and 10.2 mW at 2.4 GHz and 5.8 GHz, respectively.

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A High-Resolution Dual-Loop Digital DLL

  • Kim, Jongsun;Han, Sang-woo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.520-527
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    • 2016
  • A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

A Continuously Tunable LC-VCO PLL with Bandwidth Linearization Techniques for PCI Express Gen2 Applications

  • Rhee, Woo-Geun;Ainspan, Herschel;Friedman, Daniel J.;Rasmus, Todd;Garvin, Stacy;Cranford, Clay
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.3
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    • pp.200-209
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    • 2008
  • This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.