• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.28-35
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• 2007

In this paper, an ultra low voltage SRAM design method based on dual-boosted cell bias technique is described. For each read/write cycle, the wordline and cell power node of the selected SRAM cells are boosted into two different voltage levels. This enhances SNM(Static Noise Margin) to a sufficient amount without an increase of the cell size, even at sub 1-V supply voltage. It also improves the SRAM circuit speed owing to increase of the cell read-out current. The proposed design technique has been demonstrated through 0.8-V, 32K-byte SRAM macro design in a $0.18-{\mu}m$ CMOS technology. Compared to the conventional cell bias technique, the simulation confirms an 135 % enhancement of the cell SNM and a 31 % faster speed at 0.8-V supply voltage. This prototype chip shows an access time of 23 ns and a power dissipation of $125\;{\mu}W/Hz$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.

• Tribology and Lubricants
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• v.33 no.2
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• pp.52-58
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• 2017

An ultra-high precise ejection process is essential in a dispensing system for fabricating various precision parts such as a semiconductor, LED, and camera module. The size of such parts has been decreasing, which implies that a precise ejecting technique is required. A phosphor-containing liquid is ejected via a dispenser using dual piezoelectric actuators that are used for generating a high-speed dispensing mechanism. The rod and nozzle continuously contact in high speed to eject the liquid. However, the high-strength filler or phosphor in the liquid causes wear on the surfaces of the rod and nozzle during the dispensing process. As a result, the ejection reliability decreases as the wear on the surfaces increases. Therefore, it is necessary to estimate the wear characteristics of the rod and nozzle via an experiment and FE analysis. Reliability rests up to 1,000 cycles are conducted under relatively severe conditions. The flow rate and surfaces roughness of the rod and nozzle are measured in each ejection cycle. The surface images and wear volume are obtained before and after the tests and the ejection reliability is confirmed by measuring the flow rate of the liquid. The experimental results show that the ejection reliability is maintained up to 1,000k cycles; these results are validated by the simulation results.

• Journal of the Korean Society of Radiology
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• v.5 no.1
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• pp.27-35
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• 2011

The purpose of this study is to examine factors that affect the bone mineral density of pre-menopause women by using the dual energy x-ray absorptionmetry, ultimately contributing to preventing women's osteoporosis that tends to be aggravated since menopause. Out of the subjects, 20.2% were suffering osteopenia. Age was found most important in estimating the level of bone mineral density. Meanwhile, the older women were, the significantly lower their bone mineral density was. It was found that taking exercise has a more positive effect on boss mineral density than not taking. Exercising in a suitable amount was helping women keep their bone mineral density better. Preferring meat to vegetarian diets were significantly affecting women's bone mineral density. Meanwhile, it was found that the shorter menstrual cycle is, the significantly lower bone mineral density is. A multi=regression analysis of bone mineral density and its related factors showed that the older women were, the significantly lower their bone mineral density was. In other words, age was found as the most risk factor of osteoporosis.

• 대한공업교육학회지
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• v.33 no.1
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• pp.249-264
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• 2008

In this dissertation, shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes and a new simulator is designed to model boron diffusion in silicon. This simulator predicts the boron distribution after ion implantation and annealing. The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a RTA(Rapid Thermal Annealing) and a FA(Furnace Annealing) process. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of sheet resistance and the simulator reproduced experimental data successfully. Therefore, proposed diffusion simulator and FA+RTA annealing method was able to applied to shallow junction formation for thermal budget. process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.11
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• pp.1462-1467
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• 2018

A number of algorithms for improving the image quality of low light images have been studied using a single image or multiple exposure images. The low light image is low in contrast and has a large amount of noise, which limits the identification of information of the subject. This paper proposes the hardware design of algorithms that improve the quality of low light image using 2 multiple exposure images taken with a dual camera. The proposed hardware structure is designed in real time processing in a way that does not use frame memory and line memory using transfer function. The proposed hardware design has been designed using Verilog and validated in Modelsim. Finally, when the proposed algorithm is implemented on FPGA using xc7z045-2ffg900 as the target board, the maximum operating frequency is 167.617MHz. When the image size is 1920x1080, the total clock cycle time is 2,076,601 and can be processed in real time at 80.7fps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.29-36
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• 2005

This paper presents the first hardware design of ARIA that KSA(Korea Standards Association) decided as the block encryption standard at Dec. 2004. The ARIA cryptographic algorithm has an efficient involution SPN (Substitution Permutation Network) and is immune to known attacks. The proposed ARIA design based on 1 cycle/round include a dual port ROM to reduce a size of circuit md a high speed round key generator with barrel rotator. ARIA design proposed is implemented with Xilinx VirtexE-1600 FPGA. Throughput is 437 Mbps using 1,491 slices and 16 RAM blocks. To demonstrate the ARIA system operation, we developed a security system cyphering video data of communication though Internet. ARIA addresses applications with high-throughput like data storage and internet security protocol (IPSec and TLS) as well as IC cards.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.53 no.1
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• pp.77-88
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• 2017

The concern on the greenhouse gas emissions is increasing globally. Especially, the greenhouse gas emission from fisheries is an important issue due to Cancun Agreements Mexico in 1992 and the Kyoto protocol in 2005. Furthermore, the Korean government has a plan to reduce the GHG emissions as 5.2% compared to the BAU in fisheries until 2020. However, the investigation on the GHG emissions from Korean fisheries has not been executed much. Therefore, the quantitative analysis of GHG emissions from Korean fishery industry is needed as the first step to find a relevant way to reduce GHG emissions from fisheries. The purpose of this research is to investigate which degree of GHG emitted from the major coastal fisheries such as coastal gillnet fishery, coastal dual purpose fishery, coastal pots fishery and coastal small scale stow net fishery. Here, we calculated the GHG emission from the fisheries using the LCA (Life Cycle Assessment) method. The system boundary and input parameters for each process level are defined for LCA analysis. The fuel use coefficients of the fisheries are also calculated according to the fuel type. The GHG emissions from sea activities by the fisheries will be dealt with. Furthermore, the GHG emissions for the unit weight of fishes are also calculated with consideration to the different consuming areas. The results will be helpful to understand the circumstances of GHG emissions from Korean fisheries.

• Journal of Astronomy and Space Sciences
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• v.19 no.2
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• pp.163-172
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• 2002

This article investigates the problem of data preprocessing for the precision orbit determination (POD) of low earth orbit satellite using GPS .aw data. Several data preprocessing algorithms have been developed to edit the GPS data automatically such that outlier deletion, cycle slip identification and correction, and time tag error correction. The GPS data are precisely edited for the accuracy of POD. Some methods of data preprocessing are restricted to the rate of the collections of the pseudorange and carrier phase measurements. This study considers the preprocessing efficiency varied with the rate, the quality of receiver and the altitude of the satellite's orbit. We also propose the proper methods in accordance with the rate for single frequency and dual frequency receivers.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.1-11
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• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.