• 센서학회지
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• 제24권1호
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• pp.10-14
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• 2015

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

• 한국표면공학회지
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• 제34권5호
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• pp.516-521
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• 2001

Dry etching of Si wafer and $SiO_2$ layers was performed using He/Cl$_2$ mixture plasma by diode-type reactive ion etcher (RIE) system. For Si etching, the Cl molecules react with the Si molecules on the surface and become chemically stable, indicating that the reactants need energetic ion bombardment. During the ion assisted desorption, energetic ions would damage the photoresist (PR) and produce the bad etch Si-profile. Moreover, we have examined the characteristics of the Cl-Si reaction system, and developed the new fabrication procedures with a $Cl_2$/He mixture for Si and $SiO_2$-etching. The developed novel fabrication procedure allows the RIE to be unexpensive and useful a Si deep etching system. Since the etch rate was proved to increase linearly with fHe and the selectivity of Si to $SiO_2$ etch rate was observed to be inversely proportional to fHe.

• 반도체디스플레이기술학회지
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• 제7권1호
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• pp.1-5
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• 2008

In this paper, we fabricated pressure difference type gas flow sensor using only dry etching technology by ICP-RIE(inductive coupled plasma reactive ion etching). The sensor's structure consists of a common shear stress type piezoresistive pressure sensor with an orifice fabricated in the middle of the sensor diaphragm. Generally, structure like diaphragm is fabricated by wet etching technology using TMAH, but we fabricated diaphragm by only dry etching using ICP-RIE. To equalize the thickness of diaphragm we applied insulator($SiO_2$) layer of SOI(Si/$SiO_2$/Si-sub) wafer as delay layer of dry etching. Size of fabricated diaphragm is $1000{\times}1000{\times}7\;{\mu}m^3$ and overall chip $3000{\times}3000{\times}7\;{\mu}m^3$. We measured the variation of output voltage toward the change of gas pressure to analyze characteristics of the fabricated sensor. Sensitivity of fabricated sensor was relatively high as about 1.5mV/V kPa at 1kPa full-scale. Nonlinearity was below 0.5%F.S. Over-pressure range of the fabricated sensor is 100kPa or more.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 추계 학술대회
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• pp.59-62
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• 2005

백색 LED 램프를 제조하는 공정에서 램프간의 전기적 개방상태의 절연상태를 유지하기 위해 사파이어 기판 위에 성장된 GaN 계 반도체 에피박막층을 제거하기 위해 유도 결합형 플라즈마 식각 공정을 이용하였다. 4 미크론의 두께를 갖는 GaN 층을 식각하는데 있어 식각 방지 마스킹 물질로 포토레지스트, $SiO_2,\;Si_{3}N_4$ 및 $Al_{2}O_3$를 시험하였다. 동일한 전력 및 가스유량상태에서 $Al_{2}O_3$만 에피층을 보호할 수 있음을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.418-418
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• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

• 한국진공학회지
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• 제16권5호
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• pp.366-370
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• 2007

밀도가 높고 주기적으로 배열된 나노 크기의 기공이 25nm 두께의 실리콘 산화막 기판위에 형성 되었다. 나노미터 크기의 패턴을 형성시키기 위해서 자기조립물질을 사용했으며 폴리스티렌(PS) 바탕에 벌집형태로 평행하게 배열된 실린더 모양의 폴리메틸메타아크릴레이트(PMMA)의 구조를 형성하였다. 폴리메틸메타아크릴레이트를 아세트산으로 제거하여 폴리스티렌만 남아있는 나노크기의 마스크를 만들었다. 폴리스티렌으로 이루어진 나노패턴의 지름은 $8{\sim}30nm$ 였고 높이는 40nm였으며, 패턴과 패턴사이의 간격은 60nm였다. 형성된 패턴을 실리콘 산화막 위에 전사시키기 위해 불소 기반의 화학 반응성 식각을 사용하였다. 실리콘 산화막에 형성된 기공의 지름은 $9{\sim}33nm$였다. 실리콘 산화막을 불산으로 제거하여 실리콘에 형성된 기공을 관찰하였고, 실리콘기판에 형성된 기공의 지름은 $6{\sim}22nm$였다. 형성된 기공의 크기는 폴리메틸메타아크릴레이트의 분자량과 관계가 있음을 알 수 있었다.

• 한국정밀공학회지
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• 제19권11호
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• pp.211-220
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• 2002

Optical disk drives read information by replacing a laser beam on the disk track. As information has become larger, the more accurate position control of a laser beam is necessary. In this paper, we report the analysis and fabrication of the micro mirror for optical disk drivers. A coupled simulation of gas flow and structural displacement of the micro mirror using the Finite-Element-Method is applied to this. The mirror was fabricated by using MEMS technology. Especially, the process using the lapping and polishing step after the bonding of the mirror and electrode plates was employed for the Process reliability. The mirror size was 2.5mm${\times}$3mm and it needed about 35V for displacement of 3.2 ${\mu}$.