• 한국산업융합학회 논문집
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• 제10권4호
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• pp.227-233
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• 2007

In case of design of a rectifier to supply high current, To select switching frequency of semiconductor switches affect absolutely the design of the LC filter value in an power conversion circuit. The conventional rectifier by using MOSFET is no use in high current equipments because of small drain-source current. To solve this problem, this paper proposes to design of high capacity rectifier by parallel driving of MOSFET in the single half bridge DC-DC converter. This method can be able to develop high current rectifier by distributed drain-source current. The proposed scheme is able to expect a decrease in size, weight and cost of production by decreasing the LC filter value and increasing maximumly the switching frequency. The validity of the proposed parallel driving strategy is verified through computer-aided simulations and experimental results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• 한국통신학회논문지
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• 제24권10A호
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• pp.1579-1587
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• 1999

게이트 길이가 $0.2\mu\textrm{m}$인 P-HEMT에 대하여 드레인 바이어스 전류의 변화 및 게이트 폭에 대해 스케일링이 가능한 잡음모델을 제안하였다. 본 논문에서는 S-파라미터를 정확히 예측하기 위하여 $\tau$를 제외한 intrinsic 파라미터는 offset를 도입하여 정규화 한 후 스케일링을 하였다. 드레인 포화전류에 대한 드레인 전류의 비율과 게이트 폭을 변수로 하는 소신호 모델 파라미터의 맞춤함수를 구하였다. 또한, 잡음 파라미터를 정확히 예측하기 위하여 진성저항 잡음 온도 $\textrm{T}_{g}$, 게이트 단 전류 잡음원 등가잡음 컨덕턴스 $\textrm{G}_{ni}$, 드레인 단 전류와 게이트 폭에 거의 관계없으며 이의 평균값은 주변온도와 유사한 값으로 $\textrm{G}_{ni}$는 회로 특성에 영향을 미치지 않을 정도로 작은 값으로 추출되었다. 그러므로, $\textrm{G}_{no}$만을 잡음 모델정수로 하는 잡음모델과 $\textrm{T}_{g}$, $\textrm{G}_{ni}$, $\textrm{G}_{no}$를 잡음 모델정수로 하는 잡음모델을 측정값과 비교하여 본 결과 Gno만을 갖는 잡음모델도 측정된 잡음 파라미터와 잘 일치하였다. 따라서, 모델 정수추출이 간단한 $\textrm{G}_{no}$만을 갖는 잡음모델은 게이트 폭과 바이어스 전류에 대해 스케일링이 가능한 실용적인 잡음모델임을 확인하였다.

• 한국전기전자재료학회논문지
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• 제21권3호
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• pp.197-202
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• 2008

In this paper, we proposed an analytical model for TFT which has series of the polycrystalline structures. An average speed is defined as carrier speed by the electric field. The effective square is suggested as the area of grain without depletion for the changed grain size. First, physical parameters such as grain size, channel lenght and trap density, have been changed to prove the validity of the average speed model and the value of the effective square has been estimated through drain-source current.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권1호
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• pp.24-29
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• 2000

We propose a simple method to control the crystallization depth of amorphous silicon (a-Si) deposited by PECVD or LPCVD during the excimer laser annealing (ELA). Employing the new method, we have formed poly-Si/a-Si double film and fabricated a new poly-Si TFT with vertical a-Si offsets between the poly-Si channel and the source/drain of TFT without any additional photo-lithography process. The maximum leakage current of the new poly-Si TFT decreased about 80% due to the highly resistive vertical a-Si offsets which reduce the peak electric field in drain depletion region and suppress electron-hole pair generation. In ON state, current flows spreading down through broad a-Si cross-section in the vertical a-Si offsets and the current density in the drain depletion region where large electric field is applied is reduced. The stability of poly-Si TFT has been improved noticeably by suppressing trap state generation in drain region which is caused by high current density and large electric field. For example, ON current of the new TFT decreased only 7% at a stress condition where ON current of conventional TFT decreased 89%.

• 한국통신학회논문지
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• 제28권7A호
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• pp.451-466
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• 2003

Untethered nodes in mobile ad-hoc networks strongly depend on the efficient use of their batteries. In this paper, we propose a new metric, the drain rate, to forecast the lifetime of nodes according to current traffic conditions. This metric is combined with the value of the remaining battery capacity to determine which nodes can be part of an active route. We describe new route selection mechanisms for MANET routing protocols, which we call the Minimum Drain Rate (MDR) and the Conditional Minimum Drain Rate (CMDR). MDR extends nodal battery life and the duration of paths, while CMDR also minimizes the total transmission power consumed per packet. Using the ns-2 simulator and the dynamic source routing (DSR) protocol, we compare MDR and CMDR against prior proposals for power-aware routing and show that using the drain rate for power-aware route selection offers superior performance results.

• Journal of Electrical Engineering and information Science
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• 제2권4호
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• pp.106-110
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• 1997

A new SOI NMOSFET with a 'LOCOS-like' shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication was tried. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3${\mu}{\textrm}{m}$ SOI devices with V\ulcorner of 0.77V and Tox=7.6nm is 360$mutextrm{A}$/${\mu}{\textrm}{m}$ at V\ulcorner\ulcorner=3.5V and V\ulcorner=2.5V. Improved breakdown characteristics were obtained and the BV\ulcorner\ulcorner\ulcorner(the drain voltage for 1 nA/${\mu}{\textrm}{m}$ of I\ulcorner at V=\ulcorner\ulcorner=0V) of the device with L\ulcorner\ulcorner=0.3${\mu}{\textrm}{m}$ under the floating body condition was as high as 3.7 V. Problems for the new scheme are also addressed and more advanced device structure based on the proposed scheme is proposed to solve the problems.

• 한국전기전자재료학회논문지
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• 제21권10호
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• pp.885-888
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• 2008

We present simulation results on DC characteristics of AlGaN/GaN HEMTs having trench shaped source/drain Ohmic electrodes. In order to reduce the contact resistance in the source and drain region of the conventional AlGaN/GaN HEMTs and thereby to increase their DC output power, we applied narrow-shaped-trench electrode schemes whose size varies from $0.5{\mu}m$ to $1{\mu}m$ to the standard AlGaN/GaN HEMT structure. As a result, we found that the drain current was increased by 13 % at the same gate bias condition and the transconductance (gm) was improved by 11 % for the proposed AlGaN/GaN HEMT, compared with those of the conventional AlGaN/GaN HEMTs.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.713-716
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• 2013

전체 채널 길이는 같지만 드레인과 게이트사이의 진성영역 길이(Lin), 드레인 및 소스의 불순물 농도, 유전율, 유전체 두께가 다른 N-채널 Tunneling FET의 특성을 비교 분석하였다. 사용된 소자는 SOI 구조의 N-채널 Tunneling FET이다. 진성영역 길이는 30~70nm, 드레인 dose 농도는 $2{\times}10^{12}cm^{-2}{\sim}2{\times}10^{15}cm^{-2}$, 소스 dose 농도는 $1{\times}10^{14}cm^{-2}{\sim}3{\times}10^{15}cm^{-2}$, 유전율은 3.9~29이고, 유전체 두께는 3~9nm이다. 소자 성능 지수는 Subthreshold slope(S-slope), On/off 전류비, 누설전류이다. 시뮬레이션 결과 진성영역 길이가 길며 드레인 농도가 낮을수록 누설전류가 감소한 것을 알 수 있었다. S-slope은 소스의 불순물 농도와 유전율이 높으며 유전체 두께는 얇을수록 작은 것을 알 수 있었다. 누설전류와 S-slope을 고려하면 N-채널 TFET 소자 설계 시 진성영역 폭이 넓으며 드레인의 불순물 농도는 낮고, 소스 농도와 유전율이 높으며 유전체 두께는 얇게 하는 것이 바람직하다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.97-98
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• 2006

High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.