• East Asian Economic Review
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• v.23 no.1
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• pp.3-26
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• 2019

This study investigates the effect of high-skilled inventor emigration rate on growth rate of the country of origin (COO). Inventor emigrants represent the human capital that can generate highly innovative work. The social network they form spurs knowledge diffusion and technology transfer back to their COOs, which in turn affects innovation and growth in their home countries. We run dynamic panel estimation for 154 countries during 1990-2011, and empirically show that a positive and statistically significant effect exists for the interaction of inventor emigration and trade. The result indicates that the direct negative impact of the brain drain can be mitigated by the positive feedback effect generated by the high-skilled inventor emigrants abroad. When coupled with an active trade policy that reinforces growth, countries can partially recoup the direct effect of the human capital loss. We stress the importance of international trade for successful technology transfer to occur, and offer insights for policies that can utilize the benefits of the rich social network of their high-skilled emigrants.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.399-399
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• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.

• ETRI Journal
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• v.34 no.6
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• pp.950-953
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• 2012

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of $550{\mu}A/{\mu}m$ and $-376{\mu}A/{\mu}m$, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is $0.05{\mu}S$ and $1.2{\mu}S$ for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

• Journal of the Korean Institute of Rural Architecture
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• v.1 no.2
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• pp.83-96
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• 1999

The Buildings and facilities of municipal Councils of fundamental autonomous organization in various regions were made on the basis of its experiences in 1950s but lacked constructional sophistication and failed to comprehend their functions, resulting in several repairs and renovations after the dedications of the buildings. They also undermined the efficiencies of the worn and was a big drain on the budget of municipal councils. Furthermore, especially after the integration of rural and urban areas. Municipal councils in urban areas couldn't accommodate the increased staffs. Thereby, They used the established councils in the cities and countries and repaired and renovated other buildings of which were permitted as offices, decreasing the eligibility of the buildings for municipal councils. The poor constructional working conditions triggered new constructions of the buildings reserved only for municipal councils. The study finds out find out about the work of municipal councils and analyzes how the municipal council buildings are used as substitutional spaces, directing which way they should go in mapping out spaces. Resultantly, It becomes basic materials in constructing municipal buildings.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.6
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• pp.459-462
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• 2019

This work presents methods for reducing overshoot voltages across the drain-source of silicon carbide (SiC) MOSFETs in grid-connected hybrid active neutral-point-clamped (ANPC) inverters. Compared with 3-level NPC-type inverter, the hybrid ANPC inverter can realize the high efficiency. However, SiC MOSFETs conduct its switching operation at high frequencies, which cause high overshoot voltages in such devices. These overshoot voltages should be reduced because they may damage switching devices and result in electromagnetic interference (EMI). Two major strategies are used to reduce the overshoot voltages, namely, adjusting the gate resistor and using a snubber capacitor. In this paper, advantages and disadvantages of these methods will be discussed. The effectiveness of these strategies is verified by experimental results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.440-443
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• 2010

We report a top-down approach based on atomic force microscopy (AFM) local anodic oxidation for the fabrication of the nano-pattern field effect transistors (FETs). AFM anodic oxidation is relatively a simple process in atmosphere at room temperature but it still can result in patterns with a high spatial resolution, and compatibility with conventional silicon CMOS process. In this work, we study nano-pattern FETs for various cross-bar distance value D, from ${\sim}0.5\;{\mu}m$ to $1\;{\mu}m$. We compare the optical characteristics of the patterned FETs and of the reference FETs based on both 2-dimensional simulation and experimental results for the wavelength from 100 nm to 900 nm. The simulated the drain current of the nano-patterned FETs shows significantly higher value incident the reference FETs from ${\sim}1.7\;{\times}\;10^{-6}A$ to ${\sim}2.3\;{\times}\;10^{-6}A$ in the infrared range. The fabricated surface texturing of photo-transistors may be applied for high-efficiency photovoltaic devices.

• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1556-1565
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• 2017

This paper depicts the design, implementation and analysis of efficient resonant based wireless power transfer (WPT) technique using three magnetic coupled coils. This work is suitable for mid ranged device due to small form factor while minimizing the loading effect. A multi turned loop size resonator is exploited for both the transmitter and receiver for longer distance. In this paper, class-E power amplifier (class-E PA) is introduced with an optimum power tracking mechanism of WPT system to enhance the power capability at mid-range with a flat gain. A robust method of finding optimum distance is derived with an experimental analysis of the designed system. In this method, the load sensitive issue of WPT is resolved by tuning coupling coefficient at considerable distances. Our designed PA with a drain efficiency of 77.8% for a maximum output of 5W is used with adopted tuning technique that improves the overall WPT system performance by 3 dB at various operating points.

• Nuclear Engineering and Technology
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• v.52 no.8
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• pp.1764-1770
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• 2020

The present work was mainly concerned with studying the operation of RC-phase shift oscillator based on MOSFET type 2N6660 under the influence of different temperature levels ranging from room temperature (25 ℃) up-to135 ℃ and gamma-irradiation up-to 3.5 kGy. In this concern, both the static (I-V) characteristic curves of MOSFET devices and the output signal of the proposed oscillator were recorded under ascending levels of both temperature and gamma-irradiation. From which, it is clearly shown that the drain current was decreased from 0.22 A, measured at 25 ℃, down to 0.163 A, at 135 ℃. On the other hand, its value was increased up-to 0.49 A, whenever the device was exposed to gamma-rays dose of 3.5 kGy. Considering RC-phase shift oscillator, the oscillation frequency and output pk-pk voltage were decreased whenever MOSFET device exposed to gamma radiation by ratio 54.9 and 91%, respectively. While, whenever MOSFET device exposed to temperature the previously mentioned parameters were shown to be decreased by ratio 2.07 and 46.2%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.12
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• pp.1140-1143
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• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFTs) for liquid crystal display that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (S/D) electrodes, gate dielectric layer, and gate electrode, respectively The $NiO_x$ S/D electrodes of which the work function is well matched to that of P3HT are deposited on a P3HT channel by electron-beam evaporation of NiO powder. The maximum saturation current of our P3HT-based TFT is about $15{\mu}A$ at a gate bias of -30 V showing a high field effect mobility of $0.079cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^5$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.