• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1438-1439
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• 2006

$Ge_{2}Sb_{2}Te_5$(GST) thin film at present is a promising candidate for a phase change random access memory (PCRAM) based on the difference in resistivity between the crystalline and amorphous phase. PCRAM is an easy to manufacture, low cost storage technology with a high storage density. Therefore today several major chip in manufacturers are investigating this data storage technique. Recently, A. Pirovano et al. showed that PCRAM can be safely scaled down to the 65 nm technology node. G. T Jeonget al. suggested that physical limit of PRAM scaling will be around 10 nm node. Etching process of GST thin ra films below 100 nm range becomes more challenging. However, not much information is available in this area. In this work, we report on a parametric study of ICP etching of GST thin films in $Cl_2$/Ar chemistry. The etching characteristics of $Ge_{2}Sb_{2}Te_5$ thin films were investigated using an inductively coupled plasma (ICP) of $Cl_2$/Ar gas mixture. The etch rate of the GST films increased with increasing $Cl_2$ flow rate, source and bias powers, and pressure. The selectivity of GST over the $SiO_2$ films was higher than 10:1. X-ray photoelectron spectroscopy(XPS) was performed to examine the chemical species present in the etched surface of GST thin films. XPS results showed that the etch rate-determining element among the Ge, Sb, and Te was Te in the $Cl_2$/Ar plasma.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.1
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• pp.65-73
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• 2007

This paper presents an on-line correction method of current measurement errors for a pure-integration-based flux estimation down to 1-Hz stator frequency. An observer-based approach is taken as one possible solution of eliminating the dc offset and the negative sequence component of unbalanced gains in the synchronous coordinate. At the same time, the positive sequence component estimation is performed by creating an error signal between a motor model reference and an estimated q-axis rotor flux established by a permanent magnet (PM) in the synchronous coordinate. The compensator utilizes a PI controller that controls the error signal to zero. The proposed technique further contains a residual error compensator to completely eliminate miscellaneous disturbances in the estimated flux. The developed algorithm has been implemented on a 1.1-kW permanent magnet synchronous motor (PMSM) drive to confirm the effectiveness of the proposed scheme.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.111-111
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• 2007

Further scaling the semiconductor devices down to low dozens of nanometer needs the extremely shallow depth in junction and the intentional counter-doping in the silicon gate. Conventional ion beam ion implantation has some disadvantages and limitations for the future applications. In order to solve them, therefore, plasma source ion implantation technique has been considered as a promising new method for the high throughputs at low energy and the fabrication of the ultra-shallow junctions. In this paper, we study about the effects of DC bias and base pressure as a process parameter. The diluted mixture gas (5% $PH_3/H_2$) was used as a precursor source and chamber is used for vacuum pressure conditions. After ion doping into the Si wafer(100), the samples were annealed via rapid thermal annealing, of which annealed temperature ranges above the $950^{\circ}C$. The junction depth, calculated at dose level of $1{\times}10^{18}/cm^3$, was measured by secondary ion mass spectroscopy(SIMS) and sheet resistance by contact and non-contact mode. Surface morphology of samples was analyzed by scanning electron microscopy. As a result, we could accomplish the process conditions better than in advance.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.255-255
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• 2010

전하 트랩형 비휘발성 메모리는 10년 이상의 데이터 보존 능력과 빠른 쓰기/지우기 속도가 요구 된다. 그러나 두 가지 특성은 터널 산화막의 두께에 따라 서로 trade off 관계를 갖는다. 즉, 두 가지 특성을 모두 만족 시키면서 scaling down 하기는 매우 힘들다. 이것의 해결책으로 적층된 유전막을 터널 산화막으로 사용하여 쓰기/지우기 속도와 데이터 보존 특성을 만족하는 Tunnel Barrier engineered Memory (TBM)이 있다. TBM은 가운데 장벽은 높고 기판과 전극쪽의 장벽이 낮은 crested barrier type이 있으며, 이와 반대로 가운데 장벽은 낮고 기판과 전극쪽의 장벽이 높은 VARIOT barrier type이 있다. 일반적으로 유전율과 밴드갭(band gap)의 관계는 유전율이 클수록 밴드갭이 작은 특성을 갖는다. 이러한 관계로 인해 일반적으로 crested type의 터널 산화막층은 high-k/low-k/high-k의 물질로 적층되며, VARIOT type은 low-k/high-k/low-k의 물질로 적층된다. 이 형태는 밴드갭이 다른 물질을 적층했을 때 전계에 따라 터널 장벽의 변화가 민감하여 전자의 장벽 투과율이 매우 빠르게 변화하는 특징을 갖는다. 결국 전계에 민감도 향상으로 쓰기/지우기 속도가 향상되며 적층된 유전막의 물리적 두께의 증가로 인해 데이터 보존 특성 또한 향상되는 장점을 갖는다. 본 연구에서는 기존의 TBM과 다른 형태의 staggered tunnel barrier를 제안한다. staggered tunnel barrier는 heterostructure의 에너지 밴드 구조 중 하나로 밴드 line up은 두 밴드들이 같은 방향으로 shift된 형태이다. 즉, 가전자대 에너지 장벽의 minimum이 한 쪽에 생기면 전도대 에너지 장벽의 maximum은 반대쪽에 생기는 형태를 갖는다. 이러한 밴드구조를 갖는 물질을 터널 산화막층으로 하게 되면 쓰기/지우기 속도를 증가시킬 수 있으며, 데이터 보존 능력 모두 만족할 수 있어 TBM의 터널 산화막으로의 사용이 기대된다. 본 연구에서 제작한 staggered TBM소자의 터널 산화막으로는 $Si_3N_4$/HfAlO (Hf:Al=1:3)을 사용하여 I-V(current-voltage), Retention, Endurance를 측정하여 메모리 소자로서의 특성을 분석하였으며, 터널 산화막의 제 1층인 $Si_3N_4$의 두께를 1.5 nm, 3 nm일 때의 특성을 비교 분석하였다.

• Journal of Environmental Health Sciences
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• v.47 no.5
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• pp.454-461
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• 2021

Background: Fish and fishery products (FFPs) unintentionally contaminated with various environmental pollutants are major exposure pathways for humans. To protect human health from the consumption of contaminated FFPs, it is essential to develop a systematic tool for evaluating exposure and risks. Objectives: To regularly, accurately, and quickly evaluate adverse health outcomes due to FFPs contamination, we developed an automated dietary exposure and risk assessment system called HERA (the Human Exposure and Risk Assessment system for chemicals in FFPs). The aim of this study was to develop an overall architecture design and demonstrate the major features of the HERA system. Methods: For the HERA system, the architecture framework consisted of multi-layer stacks from infrastructure to fish exposure and risk assessment layers. To compile different contamination levels and types of seafood consumption datasets, the data models were designed for the classification codes of FFP items, contaminants, and health-based guidance values (HBGVs). A systematic data pipeline for summarizing exposure factors was constructed through down-scaling and preprocessing the 24-hour dietary recalls raw dataset from the Korea National Health and Nutrition Examination Survey (KNAHES). Results: According to the designed data models for the classification codes, we standardized 167 seafood items and 2,741 contaminants. Subsequently, we implemented two major functional workflows: 1) preparation and 2) main process. The HERA system was developed to enable risk assessors to accumulate the concentration databases sustainably and estimate exposure levels for several populations linked to seafood consumption data in KNAHES in a user-friendly manner and in a local PC environment. Conclusions: The HERA system will support policy-makers in making risk management decisions based on a nation-wide risk assessment for FFPs.

• Journal of Climate Change Research
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• v.8 no.2
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• pp.171-175
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• 2017

The purpose of the farmstead-specific early warning service system for weather risk management is to develop custom-made risk management recommendations for individual farms threatened by climate change and its variability. This system quantifies weather conditions into a "weather risk index" that is customized to crop and its growth stage. When the risk reaches the stage where it can cause any damage to the crops, the system is activated and the corresponding warning messages are delivered to the farmer's mobile phone. The messages are sent with proper recommendations that farmers can utilize to protect their crops against potential damage. Currently, the technology necessary to make the warning system more practical has been developed, including technology for forecasting real-time weather conditions, scaling down of weather data to the individual farm level and risk assessments of specific crops. Furthermore, the scientific know-how has already been integrated into a web-based warning system (http://new.agmet.kr). The system is provided to volunteer farmers with direct, one-on-one weather data and disaster warnings along with relevant recommendations. In 2016, an operational system was established in a rural catchment ($1,500km^2$) in the Seomjin river basin.

• Journal of Sensor Science and Technology
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• v.30 no.6
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• pp.436-440
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• 2021

The impact of the gate length (L_g) on the DC and high-frequency characteristics of indium-rich In_0.8Ga_0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (L_SD) of 0.8 ㎛ with different values of L_g ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (V_T) roll-off behavior against L_g was observed clearly, and the maximum transconductance (g_{m_max}) improved as L_g scaled down to 19 nm. In particular, the device with an L_g of 19 nm with an L_SD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a g_{m_max} of 2.5 mS/㎛, On resistance (R_ON) of 261 Ω·㎛, current-gain cutoff frequency (f_T) of 738 GHz, and maximum oscillation frequency (f_max) of 492 GHz. The results indicate that the reduction of L_g to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

• Journal of the Korean Recycled Construction Resources Institute
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• v.6 no.4
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• pp.297-303
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• 2018

With the changing trend of the building construction to high rising and large scaling, the underground structure has been increased, and its usage also increased and variety. Hence, to protect the underground structure against underground water, various water proofing methods has been developed. Among the many water proofing methods, the combined water proofing method using both asphalt seal and sheet has been widely used to secure the sufficient performance and decrease the construction failure. However, during the summer period of extremely high temperature conditions, the asphalt sealing materials were separated and leaked into the structure. Therefore, the aim of the research is to provide the quality standard of asphalt sealing material based on the various temperature changes depending on seasons. According to the experimental results, the temperature of the sealing materials applied on the slab was increased up to $54^{\circ}C$ which was $3^{\circ}C$ higher than the structure temperature of $51^{\circ}C$. Based on the melting test for asphalt sealing materials applied on the outside wall of the structure, in the case of water-dispersing typed materials showed significant melting down due to its slow evaporation and low viscosity. Furthermore, from the accelerated test conducted indoor conditions, a solvent-type and water-dispersing typed materials showed significant melting down due to their low viscosity and melting point in ambient conditions. Based on these results, viscosity and melting point are found as the important factors on asphalt sealing materials' quality, and it is necessary to designate the quantitative level of the viscosity and melting point for quality control.