• Transactions of Materials Processing
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• v.11 no.5
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• pp.439-446
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• 2002

This study presents a new computational model to analyze the grain deformation in a polycrystalline aggregate in a discrete manner and based directly in the underlying physical micro-mechanisms. When scaling down a metal forming process, the dimensions of the workpiece decrease but the microstructure of the workpiece remains the similar. Since the dimensions of the workpiece are very small, the microstructure especially the grain size will play an important role in micro forming, which is called size effects. As a result, specific characteristics have to be considered for the numerical analysis. The grains and grain boundary elements are introduced to model individual grains and grain boundary facets, respectively, to consider the size effects in the micro forming. The constitutive description of the grain elements accounts for the rigid-plastic and the grain boundary elements for visco-elastic relationships. The capability of the proposed approach is demonstrated through application of grain element and grain boundary element in the micro forming.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.156-156
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• 2010

최근 휴대용전자기기의 급격한 수요증가로 인하여 고성능 저전력 비휘발성메모리에 대한 관심이 크게 증가되고 있다. 다양한 비휘발성 메모리중에 상변화메모리는 고집적성과 저전력등의 장점을 가져 현재 가장 유망한 차세대 비휘발성 메모리로 각광받고 있고 일부 상용화가 진행되고 있다. 현재 상변화 메모리의 주된 연구 방향은 sub-40nm 크기에서 물리적, 전기적, 열적 scaling down에 대한 내용이며 주로 새로운 상변화 물질을 개발하여 이러한 문제점을 극복하려고 연구가 진행되고 있다. 하지만 이러한 상변화 물질의 나노급 특성은 물리적, 전기적, 열적 특성이 복합적으로 나타나고 나노급 소자 제작이 어렵기때문에 많은 연구가 진행되지 못했다. 본 연구에서는 나노임프린트 리소그래피 기술과 c-AFM 기술을 통하여 다양한 나노급 상변화 물질의 물리적, 전기적, 열적 특성에 대해 연구를 진행하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• Nuclear Engineering and Technology
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• v.29 no.3
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• pp.186-195
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• 1997

When asymmetric thermal-hydraulic conditions occur between cold legs, the core inlet temperature will be nonuniform if the coolant is not mixed perfectly in the lower plenum. These uneven core inlet conditions may induce the change in core power distribution. Thus realistic prediction of thermal mixing is important in such abnormal conditions. In this study, reactor internals, which are scaled down as to conserve the flow area ratio, are set up in the model of KORI Unit 1 with the scaling factor of 1/710 by volume and coolant temperatures are measured beneath the lower core plate. Based on experimental results, the ability of COMMIX-1B code to simulate the coolant mixing phenomena in the lower plenum is estimated. The results show that complete mixing never occurs in any conditions and the mixing pattern is characterized according to the plant type.

• Proceedings of the Safety Management and Science Conference
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• 2013.04a
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• pp.321-327
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• 2013

실리콘 기반의 반도체 산업은 Moore Rule에 따른 집적도 향상에 힘입어 눈부시게 발전해 왔다. 그러나, 최근 최소 선 폭 수준이 10nm에 다다르면서 공정의 난이도는 한계에 다다랐으며, 한계를 극복하기 위해서는 폭발적인 비용 투입만으로도 확신할 수 없기 때문에 선 폭 미세화 (Scaling Down)를 통한 집적도 향상은 더 이상 비용/성능 측면에 효율적이지 못하다. 이러한 상황으로 인해 반도체 업체들은 한계를 극복하기 위한 여러 가지 방법을 강구하고 있는 실정이다. 이러한 (개발 난이도 증가, 소형화, 경량화, 고집적화에 대한 고객 요구 증대) 한계를 해결하기 위하여, 크게 3가지 관점에서 지속적으로 연구가 이루어 지고 있다. 여기서는 현재 가장 활발한 연구가 이루어지고 있으며, 가장 대응이 용이한 PKG 신기술 개발에 대하여 다루고자 한다.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.107-112
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• 2011

This paper is for improving the RF frequency performance of a fabricated 100nm ${\Gamma}$-gate MHEMT, scaling down vertically for the epitaxy-structure layers of the device. Hydrodynamic simulation parameters are calibrated for the fabricated MHEMT with the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}$As heterostructure grown on the GaAs substrate. With these calibrated parameters, simulations for the vertically-scaled epitaxial layers of the device are performed and analyzed for DC/RF characteristics, including the quantization effect due to the thickness reduction of InGaAs channel layer. A newly designed epitaxy-structure device shows higher extrinsic transconductance, $g_m$ of 1.556 S/mm, and higher frequency performance, $f_T$ of 222.5 GHz and $f_{max}$ of 849.6 GHz.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.15-16
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• 2006

In this paper, we propose an adaptive SLM scheme based on peak observation for PAPR reduction of OFDM signals. The proposed scheme is composed of three steps: peak scaling, sequence selection, and SLM procedures. In the first step, the peak signal samples in the IFFT outputs of the original input sequence are scaled down. In the second step, the sub-carrier positions where power difference between the original input sequence and the FFT outputs of the scaled signal is large, are identified. Then, the phase sequences which have the maximum number of phase-reversed sequence words only for these positions, are selected. Finally, only using the selected phase sequences, the generic SLM procedure is performed for the original input sequence. Simulation results reveal that the proposed adaptive SLM remarkably reduces the complexity in terms of IFFT and PAPR calculations than the conventional SLM, while maintaining the PAPR reduction performance.

• Computers and Concrete
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• v.2 no.6
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• pp.481-498
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• 2005

A wavelet based approach is proposed for structural damage detection in beams, plate and delamination of composite plates. Wavelet theory is applied here for crack identification of a beam element with a transverse on edge non-propagating open crack. Finite difference method was used for generating a general displacement equation for the cracked beam in the first example. In the second and third example, damage is detected from the deformed shape of a loaded simply supported plate applying the wavelet theory. Delamination in composite plate is identified using wavelet theory in the fourth example. The main concept used is the breaking down of the dynamic signal of a structural response into a series of local basis function called wavelets, so as to detect the special characteristics of the structure by scaling and transformation property of wavelets. In the light of the results obtained, limitations of the proposed method as well as suggestions for future work are presented. Results show great promise of wavelet approach for damage detection and structural health monitoring.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.1
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• pp.36-43
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• 2003

This paper presents an optimal tuning method for Fuzzy Logic Controller (FLC) of current controller for HVDC using Genetic Algorithm(GA). GA is probabilistic search method based on genetics and evolution theory. The scaling factors of FLC are tuned by using real-time GA. The proposed tuning method is applied to the scaled-down HVDC simulator at Korea Electrotechnology Research Institute(KERI). Experimental result shows that disturbances are well-damped and the dynamic performances of FLC have the better responses than those of PI controller for small and large disturbances such as ULTC tap change, reference DC current change and DC ground fault.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.6
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• pp.1214-1218
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• 2006

This paper presents method to speed up processing time in construction of panoramic images. The method based on invariant feature uses image down-scaling and image edge information. Reducing image size and applying feature descriptor to image portions superimposed with edge causes to reduce the number of features and to improve processing speed. In the experiments, it was shown that the proposed method was 3.26$\sim$13.87% shorter in processing time than the exiting method fer 24-bit color images of 640$\times$480 size.