• Transactions on Electrical and Electronic Materials
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• 제14권6호
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.76-81
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• 2007

Threshold voltage ($V_{th}$) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length ($x_h$) in the channel which is related to the barrier lowering becomes very important. A fitting parameter ${\delta}_w$ was introduced semi-empirically with the fin body width and body doping concentration for higher accuracy. The $V_{th}$ model predicted well the $V_{th}$ behavior with fin body thickness, body doping concentration, and gate length. Our compact model makes an accurate $V_{th}$ prediction of DG devices with the gate length up to 20-nm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.511-515
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• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

• 대한전자공학회논문지SD
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• 제47권8호
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• pp.13-22
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• 2010

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET은 기존의 bulk-MOSFET에 비해 향상된 채널 제어능력을 가지며, front-게이트와 back-게이트를 서로 다른 전압으로 구동가능하다는 이점을 가진다. 따라서, 이를 이용한 회로설계는 4-terminal의 자유도를 이용함으로써 회로성능의 향상 뿐 아니라 집적도 향상을 기대할 수 있다. 본 논문에서는 IGM-DG MOSFET의 장점을 이용하여 TIA, feedforward LA, 및 OB로 구성된 15Gb/s 광수신기를 설계하고, HSPICE 시뮬레이션을 통한 회로성능 검증 및 외부환경과 소자의 특성변화에 따른 안정성을 검증하였다.

• Journal of information and communication convergence engineering
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• 제9권5호
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• pp.583-586
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• 2011

In this paper, subthreshold swing characteristics have been presented for double-gate MOSFETs, using the analytical model based on series form of potential distribution. Subthreshold swing is very important factor for digital devices because of determination of ON and OFF. In general, subthreshold swings have to be under 100mV/dec. The channel length $L_g$ is varied from 30nm to 100nm, and channel thickness $t_{si}$ from 15 to 20nm according to channel length, and oxide thickness 5nm to investigate subthreshold swing. The doping of channel is fixed with $10^{16}cm^{-3}$ p-type. The results show good agreement with numerical simulations, confirming this model.

• 전기전자학회논문지
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• 제19권4호
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• pp.514-519
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• 2015

본 논문에서는 이중 게이트 junctionless MOSFET 의 성능 최적화를 위하여 다중 게이트 형태를 적용하여 평가한다. 금속 게이트들 사이의 일함수가 서로 다르므로 다중 게이트 구조를 적용할 경우 금속게이트 길이에 따라 소스와 드레인 주변의 전위를 조절할 수 있다. 동작 전류와 누설 전류 그리고 동작 전압은 게이트 구조에 의해 조절이 가능하며 이로 인한 동작 특성 최적화가 가능하다. 본 연구에서는 반도체 소자 시뮬레이션을 통하여 junctionless MOSFET 의 최적화를 구현하고 분석하는 연구를 수행 한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.897-900
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• 2005

RF linearity of double-gate MOSFETs is investigated using accurate two-dimensional simulations. The linearity has been analyzed using the Talyor series. Transconductance is dominant nonlinear source of CMOS. It is shown that DGMOSFET linearity can be improved by a careful optimization of channel thickness, gate oxide thickness, gate length, overlap length and channel doping concentration. The minimum $P_{IP3}$ data are compared in each case. It is shown that DG-MOSFET linearity can be improved by a careful optimization of channel thickness, gate oxide thickness, gate length, overlap length and channel doping concentration..

• 한국전기전자재료학회논문지
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• 제31권3호
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• pp.146-151
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• 2018

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.130-133
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• 2010

This paper presents a study of the influence of variation of counter doping thickness on short channel effect in symmetric double-gate (DG) nano MOSFETs. Short channel effects are estimated from the computed values of current-voltage (I-V) characteristics. Two dimensional Quantum transport equations and Poisson equations are used to compute DG MOSFET characteristics. We found that the transconductance ($g_m$) and the drain conductance ($g_d$) increase with an increase in p-type counter-doping thickness ($T_c$). Very high value of transconductance ($g_m=38\;mS/{\mu}m$) is observed at 2.2 nm channel thickness. We have established that the threshold voltage of DG MOSFETs can be tuned by selecting the thickness of counter-doping in such device.

• EDISON SW 활용 경진대회 논문집
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• 제3회(2014년)
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• pp.457-458
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• 2014

In this paper, quantum mechanical simulations of the double-gate ultra-thin body (DG-UTB) MOSFETs are performed according to the International Technology Roadmap of Semiconductors (ITRS) specifications planned for 2020, to devise the way for on-current ($I_{on}$) improvement. We have employed non-equilibrium Green's function (NEGF) approach and solved the self-consistent equations based on the parabolic effective mass theory [1]. Our study shows that the [100]/<001> Ge and GaSb channel devices have higher $I_{on}$ than Si channel devices under the body thickness ($T_{bd}$) <5nm condition.