• 전자공학회논문지C
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• 제34C권6호
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• pp.28-36
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• 1997

In this work, a highly linear video-speed CMOS current-mode digital-to-analog converter (DAC) is proposed. A newswitching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral nonlinearities (INL). The proposed DAC is designed to operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with degliching circuits developed in this work. The prototype dAC was implemented in a LG 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral nonlinearities are less than .+-. LSB and .+-.0.8LSB respectively. The DAC dissipates 75mW at a 3V single power supply and occupies a chip area of 2.4 mm * 2.9mm.

• 전자공학회논문지C
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• 제34C권12호
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• Journal of Information Display
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• 제5권2호
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• pp.1-5
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• 2004

We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA ($240{\times}320$) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1324-1326
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• 2006

In this study, an integrated microelectrode array was fabricated on glass slide using microfabrication technology. Probe DNAs consisting of mercaptohexyl moiety at their 5-end were spotted on the gold electrode using micropipette or DNA arrayer utilizing the affinity between gold and sulfur. Cyclic voltammetry in 5mM ferricyanide/ferrocyanide solution at 100 mV/s confirmed the immobilization of probe DNA on the gold electrodes. When several DNAs were detected electrochemically, there was a difference between target DNA and control DNA in the anodic peak current values. It was derived from specific binding of Hoechst 33258 to the double stranded DNA due to hybridization of target DNA. It suggested that this DNA chip could recognize the sequence specific genes. It suggested that multichannel electrochemical DNA microarray is useful to develop a portable device for clinical gene diagnostic system.

• International journal of advanced smart convergence
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• 제10권3호
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• Journal of the Korean Wood Science and Technology
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• 제17권4호
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• pp.57-69
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• 1989

Roughage feeds were produced from Hyun-aspen (Populus alba $\times$ p. glandulosa) by steaming-defibration and steaming-explosion. The objectives of this work were to find proper conditions for the treatment of Hyun-aspen by analyzing the compositional change and digestibility and to investigate the change of physical properties of exploded woods. The results of this work were as follows; 1. The method of steaming-de fibration gave the best producing rate of feedstuffs when the chips were steamed (9kg/$cm^2$ under the pressure) for 10 minutes. The yield and the digestibility of feedstuffs were 84.2% and 38.1%, respectively. It is the merit of this method that feedstuffs manufactured by this method was uniformity in particle size, and facilities of fiberboard factory could be used directly, 2. For defibration of the chip by explosion, the proper condition was steamed under the pressure (20kg/$cm^2$) for 4 minutes. The yield and the digestibility of feedstuffs were 93.4% and 68.1%, respectively. The feedstuffs produced under these conditions had higher nutritional quality than rice straw and this method was considered as the best for making feedstuffs from Hyun-aspen chip. But it is defect that exploded feedstuffs was ununiformity in particle size and had unique odor. The physical properties of the feedstuffs were investigated by a light microscope and a TEM. The feedstuffs produced under the low pressure (20 kg/$cm^2$) still maintained the structure of fibers. However, the feedstuffs produced under the high pressure (28 kg/$cm^2$) resulted in higher de fib ration than these prepared under the low pressure. The highly defibrated feedstuffs recombined with solublized lignin. The crystallinity of feedstuffs was increased by 10% and micelle width increased double after treatment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.322-330
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• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.35-42
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• 2004

본 논문에서는 저 전력, 고속 동작을 위하여 트랜지스터 차동쌍 폴딩 회로를 사용하는 CMOS 폴딩 ADC를 설계하였다. 본 논문에서는 제안한 트랜지스터 차동쌍 폴딩 회로에 대한 동작원리와 기존의 폴딩 회로에 비해 어떤 장점을 가지고 있는지 설명한다. 이 회로를 적용하여 설계한 ADC에서는 폴딩신호를 처리하기 위하여 16 개의 정밀한 전압비교기와 32 개의 인터폴레이션 저항을 사용하므로 저 전력, 고속동작이 가능하고, 작은 칩 면적으로 제작할 수 있다. 설계공정은 0.25㎛ double-poly 2metal n-well CMOS 공정을 사용하였다. 모의실험결과 2.5V 전원전압을 인가하고 250MHz의 클럭 주파수에서 45mW의 전력을 소비하였으며 측정값을 통하여 계산된 INL은 ±0.15LSB, DNL은 ±0.15LSB, SNDR은 10MHz 입력신호에서 50dB로 측정되었다.

• 센서학회지
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• 제5권4호
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• pp.41-46
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• 1996

변압기 절연유중 용존수소를 감지하기 위해 Pd/Pt 게이트 MISFET 센서를 제조하고 그 특성을 조사하였다. 동일 칩안에 내장형 히터와 온도측정용 다이오드를 제조하고 MISFET의 전압 드리프트를 줄이기 위해 차동형구조로 하였다. 수소유입 드리프트를 줄이기 위해, 양쪽 FET의 게이트 절연층을 실리콘 산화막과 실리콘 질화막의 2중 구조로 하였다. 수소감지막의 블리스터를 줄이기 위해 Pd/Pt 2중 금속층을 증착하였다. 제조된 센서의 변압기 절연유에 대한 수소감지 특성은 40mV/10ppm 감도와 0.14mV/day 안정도를 보였다.

• 한국정보통신학회논문지
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• 제8권4호
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• pp.826-832
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• 2004

본 논문에서는 VLSI의 내장 회로로 사용하기에 적합한 CMOS 8 비트 폴딩-인터폴레이팅 AD 변환기를 설계하였다. 폴딩 AD 변환기의 비선형성을 개선하기 위하여 입력신호의 폴딩-인터폴레이팅에 의한 신호처리가 차례로 2 번 반복되는 2 단 구조를 사용하였다. 이 구조에서는 2 번째 폴딩 회로로서 트랜지스터 차동쌍을 이용한다. 2 단 폴딩 ADC는 디지틸 출력을 얻기 위한 전압비교기와 저항의 개수를 현저히 줄일 수 있으므로 칩 면적, 소비전력, 동작속도 둥에서 많은 장점을 제공한다. 설계공정은 0.25$\mu$m double-poly 2 metal n-well CMOS 공정을 사용하였다. 모의실험결과 2.5V 전원 전압을 인가하고 250MHz의 샘플링 주파수에서 45mW의 전력을 소비하였으며 INL과 DNL은 각 각 $\pm$0.2LSB, SNDR은 10MHz 입력신호에서 45dB로 측정되었다.