• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.30-40
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• 2002

A 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard $0.35\mu\textrm$ CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.246-251
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• 2014

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA ($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.37-42
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• 1997

A new temperature and supply-insensitive CMOS current reference circuit was designed and tested. Te temperature insensuitivity was achieved by eliminating the mobility dependence term through the multiplication of two current components, one which is proportional to mobility and the other which is inversely proportional to mobility, by using a newly designed CMOS square root circuit. The CMOS sqare root circuit was derived from its bipolar counterpart by operating the MOS transistors in the subthreshold region. The supply insensitivity was achieved by using an internal voltage generator. Te test chip was designed ans sent out for fabrication by using a 2.mu.m double-poly double-metal n-well CMOS technology. When an external voltage source was used for the square root circuit, the maximum variation and the average temperature sensitivity were measured to be 3% and 21.4ppm/.deg.C, respectively, for the temperature range of -15~130.deg.C. The maximum current variation with supply voltage was measured to be 3% within the commerical supply voltage range of 4.5~5.5V at 30.deg. C.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.10
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• pp.849-856
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• 2012

Chip on board type white light emitting diode on metal core printed circuit board with high thixotropy silicone is fabricated by vacuum printing encapsulation system. Encapsulant is chosen by taking into account experimental results from differential scanning calorimeter, shearing strength, and optical transmittance. We have observed that radiant flux and package efficacy are increased from 336 mW to 450 mW and from 11.9 lm/W to 36.2 lm/W as single dome diameter is varied from 2.2 mm to 2.8 mm, respectively. Double encapsulation structure with 2.8 mm of dome diameter shows further significant enhancement of radiant flux and package efficacy to 667 mW and 52.4 lm/W, which are 417 mW and 34.8 lm/W at single encapsulation structure, respectively.

• ETRI Journal
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• v.37 no.3
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• pp.523-532
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• 2015

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are $28.3{\mu}m$, $31.7{\mu}m$, and $26.3{\mu}m$, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.264-271
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• 2011

ILS(Instrument Landing System) is the international standard system for approach and landing guidance. ILS was adopted by ICAO(International Civil Aviation Organization) in 1947 and is currently being used in commercial systems. To design the digital transmitter and receiver modules that can be mounted in the integrated ILS, we propose the digital design methods of digital double AM modulator and demodulator using FPGA chip, DDS(Direct Digital Synthesizer) for generation of sampling clock, demodulator of DDC(Digital Down Converter) structure, and spectrum analyzer using DSP chip. We demonstrate the efficiency of the proposed design method through experiments using developed transmitter and receiver modules. This system can be used as a high-performance commercial system.

• Korea-Australia Rheology Journal
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• v.17 no.4
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• pp.207-215
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• 2005

We present a finite difference solution for electrokinetic flow in rectangular microchannels encompassing Navier's fluid slip phenomena. The externally applied body force originated from between the nonlinear Poisson-Boltzmann field around the channel wall and the flow-induced electric field is employed in the equation of motion. The basic principle of net current conservation is applied in the ion transport. The effects of the slip length and the long-range repulsion upon the velocity profile are examined in conjunction with the friction factor. It is evident that the fluid slip counteracts the effect by the electric double layer and induces a larger flow rate. Particle streak imaging by fluorescent microscope and the data processing method developed ourselves are applied to straight channel designed to allow for flow visualization of dilute latex colloids underlying the condition of simple fluid. The reliability of the velocity profile determined by the flow imaging is justified by comparing with the finite difference solution. We recognized the behavior of fluid slip in velocity profiles at the hydrophobic surface of polydimethylsiloxane wall, from which the slip length was evaluated for different conditions.

• Current Optics and Photonics
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• v.8 no.4
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• pp.399-405
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• 2024

In this paper, an optical modulator based on monolayer graphene and triple-layer black phosphorus (BP) heterojunction in the optical communication band range is designed. The influences of geometric parameters, chemical potential, BP orientation and dispersion on the fundamental mode of this modulator were determined in detail by the finite-difference time-domain (FDTD) method. Using appropriate geometric parameter settings, the extinction ratio of this proposed modulator is 0.166 dB, while the modulator with a working length of 3 ㎛ can realize a 0.498 dB modulation depth. The 3-dB bandwidth of this modulator could achieve up to 2.65 GHz with 27.23 fJ/bit energy consumption. The extinction ratio and bandwidth of the proposed modulator increased by 66% and 120.83%, respectively, compared to the monolayer graphene-based ridge-type waveguide modulator. Energy consumption was reduced by 97.28%, compared to a double-layer graphene-based modulator.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.505-516
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• 2000

Cellular Neural Networks(CNN) is a nonlinear information-processing system that has a locally connected characteristic and is widely used in the real-time high speed image processing. In this paper, a practical system approach of time-multiplexing CNN implementations suitable for processing large and complex images using small CNN arrays is presented and $6\times6$ CNN hardware is designed for the processing of a large image. While previous implementations are mostly suitable for black and white applications because of the thresholded outputs, our approach is especially suitable for applications in gray image processing due to the analog nature of the state node. CNN chip is designed using a 0.65${\mu}{\textrm}{m}$ 2P2M(double poly, double metal) N-Well CMOS process technology. It contains about 15,400 devices on an area of about $1.85\times1.75$ md. The designed $6\times6$ CNN is tested for the edge detection of a large image input and it's performance is verified.