• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.9
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• pp.833-839
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• 2011

This paper has suggested a technique for measuring VSWR at 1.8 GHz band for various modulated signals. By using directional coupler the power of incident and reflected wave is measured, and in order to minimize the size and cost of the measuring circuit, a SPDT(Single Pole Double Throw) switch is adopted to realize the circuit with just one detector and one A/D(Analog to Digital) converter. MCU(Micro Control Unit) is used to calculate the voltage reflection coefficient and VSWR, and the measured VSWR error has improved by approximately 0.2 with applying a simple bubble sorting algorithm to reduce the measurement error, the MCU process time and load.

• Journal of Power Electronics
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• v.10 no.4
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• pp.342-350
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• 2010

Randomizing the switching frequency (RSF) to reduce the electromagnetic interference (EMI) of switching power converters is a well-known technique that has been previously discussed. The randomized pulse position (RPP) technique, in which the switching frequency is kept fixed while the pulse position (the delay from the starting of the switching cycle to the turn-on instant within the cycle) is randomized, has been previously addressed in the literature for the same purpose. This paper presents a double-hybrid technique (DHB) for EMI reduction in dc-dc switching regulators. The proposed technique employed both the RSF and the RPP techniques. To effectively spread the conducted-noise frequency spectrum and at the same time attain a satisfactory output voltage quality, two parameters (switching frequency and pulse position) were randomized, and a third parameter (the duty ratio) was controlled by a digital compensator. Implementation was achieved using field programmable gate array (FPGA) technology, which is increasingly being adopted in industrial electronic applications. To evaluate the contribution of the proposed DHB technique, investigations were carried out for each basic PWM, RPP, RSF, and DHB technique. Then a comparison was made of the performances achieved. The experimentally investigated features include the effect of each technique on the common-mode, differential-mode, and total conducted-noise characteristics, and their influence on the converter’s output ripple voltage.

• Ocean Systems Engineering
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• v.2 no.4
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• pp.297-314
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• 2012

Power-take-off through inner dynamic system inside a floating buoy is suggested. The power take-off system is characterized by mass, stiffness, and damping and generates power through the relative heave motion between the buoy and inner mass (magnet or amateur). A systematic hydrodynamic theory is developed for the suggested WEC and the developed theory is illustrated by a case study. A vertical truncated cylinder is selected as a buoy and the optimal condition of the inner dynamic system for maximum PTO (power take off) through double resonance for the given wave condition is systematically investigated. Through the case study, it is seen that the maximum power can actually be obtained at the optimal spring and damper condition, as predicted by the developed WEC theory. However, the band-width of high performance region is not necessarily the greatest at the optimal (maximum-power-take-off) condition, so it has to be taken into consideration in the actual design of the WEC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.613-623
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• 2000

Digital TV tuner for 8-VSB modulation was developed with satisfying the requirements of ATSC. The double frequency conversion and the active tracking filter in the front-end were used to reduce interference of the adjacent channels and multi-channels, which suppress If beat and image band. However, it was impossible to get frequency mapping between tracking filter and first VCO(Voltage Controlled Oscillator) in the double conversion digital TV tuner differing from conventional NTSC tuner. This paper, therefore, suggests the available structure and a new method for automatic frequency selection by obtaining the mapping of frequency characteristic over tracking voltage and the combined hardware which compose of Micro-controller, EEPROM, D/A(Digital-to-Analog Converter), OP amp and switch driver to solve above problems.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.249-254
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• 2013

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

• Food Science and Biotechnology
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• v.14 no.4
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• pp.554-557
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• 2005

As a device for taste sensation, an 8-channel taste evaluation system was prepared and applied for discriminant analysis of marketed liquor. The biomimetic polymer membranes for the system were prepared through a casting procedure by employing polyvinyl chloride, bis (2-ethylhexyl)sebacate as plasticizer and electroactive materials such as valinomycin in the ratio of 33:66:1, and were separately attached over the sensitive area of ion-selective electrodes to construct the corresponding taste sensor array. The sensor array in conjunction with a double junction reference electrode was connected to a high-input impedance amplifier and the amplified sensor signals were interfaced to a personal computer via an A/D converter. When the signal data from the sensor array for 3 groups of marketed liquor like Maesilju, Soju and beer were analyzed by principal component analysis after normalization, it was observed that the 1st, 2nd and 3rd principal component were responsible for most of the total data variance, and the analyzed liquor samples were discriminated well in 2 dimensional principal component planes composed of the 1st-2nd and the 1st-3rd principal component.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.10-16
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• 2016

In this paper, a design for a fully digital voltage sensor using a 32-nm fin-type field-effect transistor (FinFET) is presented. A new characteristic of the double gate p-type FinFET (p-FinFET) is examined and proven appropriate for sensing voltage variations. On the basis of this characteristic, a novel technique for designing low-power voltage-to-time converters is presented. Then, we develop a digital voltage sensor with a voltage range of 0.7 to 1.1V at a 50-mV resolution. The performance of the proposed sensor is evaluated under a range of voltages and process variations using Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, and the sensor is proven capable of operating under ultra-low power consumption, high linearity, and fairly high-frequency conditions (i.e., 100 MHz).

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.399-400
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• 2016

최근 DC 전력 전송의 관심이 고조되면서 DC-transformer(DCT)-type 컨버터에 대한 연구가 활발히 진행되고 있다. 이러한 DCT 컨버터는 고효율 동작이 가능하나, 부하에 따라 출력 전압 강하가 일어나는 단점을 갖고 있다. 따라서 본 논문에서는 보조용 공진 컨버터를 사용해 DCT의 부하 증가에 따른 전압 강하를 보상할 수 있는 새로운 구조의 컨버터 시스템을 제안한다. 또한 제안된 이중구조 공진형 컨버터의 타당성을 검증하기 위해 Psim을 이용하여 시뮬레이션을 행하였다.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.32-36
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• 1990

LPM is a characterized motor to reciprocate linear motion for the office automation(OA), the factory automation(FA) and the field of information instruments because it can generate direct drive without any mechanical converter. For the design and analysis of permanent magnet type linear, pulse motor, it is therefore necessary to investigate the characteristics of magnetic flux distribution, static and dynamic thrust force, normal force, etc, by analyzing its magnetic circuit. This paper describes various useful methods for improving the characteristics of LPM. And these method is adopted on the PM and flat type, double side 2-phase 8-pole LPM.