• 한국전자통신학회논문지
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• 제13권4호
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• pp.721-728
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• 2018

본 논문은 다양한 구조의 선형 블록 오류정정코드를 소개하고, 이를 회로로 구현하여 비교 분석한 결과를 보여주고 있다. 메모리 시스템에서는 잡음 전력으로 인한 비트 오류를 방지하기 위해 ECC(: Error Correction Code)가 사용되어 왔다. ECC의 종류에는 SEC-DED(: Single Error Correction Double Error Detection)와 SEC-DED-DAEC(: Double Adjacent Error Correction)가 있다. SEC-DED인 Hsiao 코드와 SEC-DED-DAEC인 Dutta, Pedro 코드를 각각 Verilog HDL을 이용해 설계 후 $0.35{\mu}m$ CMOS 공정을 사용해 회로로 합성하였다. 시뮬레이션에 의하면 SEC-DED회로는 인접한 두 개의 비트 오류를 정정하지 못하지만 적은 회로 사용면적과 빠른 지연 시간의 장점이 있으며, SEC-DED-DAEC 회로의 경우 Pedro 코드와 Dutta 코드 간에는 면적, 지연 시간의 차이가 없으므로 오류 정정률이 개선된 Pedro 코드를 사용하는 것이 더 효율적임을 알 수 있다.

• 한국정보통신학회논문지
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• 제26권10호
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• 한국정보통신학회논문지
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• 제26권11호
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• pp.1747-1750
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• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.85-88
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• 2001

In this paper, we propose a retransmission based error control scheme in which a stop-and-wait ARQ is simultaneously performed in two adjacent layers for the node-to-node error control. We develop an analytical numerical method to calculate the probability of error remains and the moments of the high layer message delay time at steady state. Using the analytical method, we investigate the performance of double-layered ARQ scheme with respect to the properties of the employed CRC codes and the characteristics of the involved channel.