• Journal of Korean Tunnelling and Underground Space Association
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• v.19 no.2
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• pp.121-141
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• 2017

The thermal analysis of an underground power conduit for electrical cables is essential to determine their current capacity with an increasing number of demands for high-voltage underground cables. The temperature rises around a buried cable, caused by excessive heat dissipation, may increase considerably the thermal resistance of the cables, leading to the danger of "thermal runaway" or damaging to insulators. It is a key design factor to develop the mechanism on thermal behavior of backfilling materials for underground power conduits. With a full-scale field test, a numerical model was developed to estimate the temperature change as well as the thermal resistance existing between an underground power conduit and backfill materials. In comparison with the field test, the numerical model for analyzing thermal behavior depending on density, moisture content and soil constituents is verified by the one-year-long field measurement.

• Journal of the Korean Magnetics Society
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• v.24 no.3
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• pp.76-80
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• 2014

Toroidal cores made of metallic powder requires large magnetic field strength up to few decade kA/m to obtain major hysteresis loop. To overcome thermal heat generation problem from large exciting current during measurement, we have employed a real time hysteresis loop tracer which can digitize and calculate B-H signals in personal computer as real time. For example, when we magnetize specimen at 10 Hz frequency, we could display hysteresis loops 10 times per second. Using the real time hysteresis loop tracer, we could measure major hysteresis loop of toroidal shape metallic powder core at maximum flux density or maximum magnetic field strength to be measured within 5 second not to significant increasement of specimen temperature due to the heat dissipation from coil windings. For the constructed hysteresis loop tracer, we could measure hysteresis loop at magnetic field strength higher than 50 kA/m for the toroidal shape specimen.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.60-68
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• 2008

This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

• Earthquakes and Structures
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• v.8 no.3
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• pp.665-679
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• 2015

The strain rate of reinforced concrete (RC) structures stimulated by earthquake action has been generally recognized as in the range from $10^{-4}/s$ to $10^{-1}/s$. Because both concrete and steel reinforcement are rate-sensitive materials, the RC beam-column joints are bound to behave differently under different strain rates. This paper describes an investigation of seismic behavior of RC beam-column joints which are subjected to large cyclic displacements on the beam ends with three loading velocities, i.e., 0.4 mm/s, 4 mm/s and 40 mm/s respectively. The levels of strain rate on the joint core region are correspondingly estimated to be $10^{-5}/s$, $10^{-4}/s$, and $10^{-2}/s$. It is aimed to better understand the effect of strain rates on seismic behavior of beam-column joints, such as the carrying capacity and failure modes as well as the energy dissipation. From the experiments, it is observed that with the increase of loading velocity or strain rate, damage in the joint core region decreases but damage in the plastic hinge regions of adjacent beams increases. The energy absorbed in the hysteresis loops under higher loading velocity is larger than that under quasi-static loading. It is also found that the yielding load of the joint is almost independent of the loading velocity, and there is a marginal increase of the ultimate carrying capacity when the loading velocity is increased for the ranges studied in this work. However, under higher loading velocity the residual carrying capacity after peak load drops more rapidly. Additionally, the axial compression ratio has little effect on the shear carrying capacity of the beam-column joints, but with the increase of loading velocity, the crack width of concrete in the joint zone becomes narrower. The shear carrying capacity of the joint at higher loading velocity is higher than that calculated with the quasi-static method proposed by the design code. When the dynamic strengths of materials, i.e., concrete and reinforcement, are directly substituted into the design model of current code, it tends to be insufficiently safe.

• Korean Journal of Materials Research
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• v.18 no.4
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• pp.169-174
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• 2008

The structural and electrical properties of amorphous $BaSm_2Ti_4O_{12}$ (BSmT) films on a $TiN/SiO_2/Si$ substrate deposited using a RF magnetron sputtering method were investigated. The deposition of BSmT films was carried out at $300^{\circ}C$ in a mixed oxygen and argon ($O_2$ : Ar = 1 : 4) atmosphere with a total pressure of 8.0 mTorr. In particular, a 45 nm-thick amorphous BSmT film exhibited a high capacitance density and low dissipation factor of $7.60\;fF/{\mu}m2$ and 1.3%, respectively, with a dielectric constant of 38 at 100 kHz. Its capacitance showed very little change, even in GHz ranges from 1.0 GHz to 6.0 GHz. The quality factor of the BSmT film was as high as 67 at 6 GHz. The leakage current density of the BSmT film was also very low, at approximately $5.11\;nA/cm^2$ at 2 V; its conduction mechanism was explained by the the Poole-Frenkel emission. The quadratic voltage coefficient of capacitance of the BSmT film was approximately $698\;ppm/V^2$, which is higher than the required value (<$100\;ppm/V^2$) for RF application. This could be reduced by improving the process condition. The temperature coefficient of capacitance of the film was low at nearly $296\;ppm/^{\circ}C$ at 100 kHz. Therefore, amorphous BSmT grown on a TiN substrate is a viable candidate material for a metal-insulator-metal capacitor.

• Journal of the Korean Ceramic Society
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• v.40 no.11
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• pp.1067-1072
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• 2003

The electrical stability of the varistor ceramics composed of Zn-Pr-Co-Cr-Dy oxides-based varistors was investigated at 0.0∼2.0 mol% Dy$_2$O$_3$ content under DC accelerated aging stress. The ceramic density was increased up to 0.5 mol% Dy$_2$O$_3$ whereas further addition of Dy$_2$O$_3$ decreased sintered ceramic density. The density sailently affected the stability due to the variation of conduction path. The nonlinearity of varistor ceramics was greatly improved above 45 in the nonlinear exponent and below nearly 1.0 ${\mu}$A by incorporating Dy$_2$O$_3$. Under 0.95 V$\_$1mA/150$^{\circ}C$/24 h stress state, the varistor ceramics doped with 0.5 mol% Dy$_2$O$_3$ exhibited the highest electrical stability, in which the variation rates of varistor voltage, nonlinear exponent, and leakage current were -0.9%, -14.4%, and +483.3%, respectively. The variation rates of relative permittivity and dissipation factor were +7.1% and +315.4%, respectively. The varistors with further addition of Dy$_2$O$_3$ exhibited very unstable state resulting in the thermal runaway due to low density.

• Journal of the Korea institute for structural maintenance and inspection
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• v.26 no.3
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• pp.84-91
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• 2022

In this study, an experimental study was conducted to analyze the hysteresis behavior according to the steel fiber aspect ratio and volume fraction of diagonally reinforced concrete coupling beams under to cyclic loading. The aspect ratio and volume fraction of the steel fibers were set as the main variables, and 4 specimens were fabricated in which the amount of transverse reinforcement of the coupling beam suggested in the domestic building structural standard was relaxed by about 53%. In the experiment, cyclic loading experiments were performed in the displacement control method in accordance with ACI 374.2R-13, and as a result of the experiment, it was found that all specimens containing steel fibers exceeded the nominal shear strength suggested by the current structural standards. As the aspect ratio of the steel fibers increased, the steel fibers prevented the buckling of the diagonal reinforcement, and the bridging effect of the steel fibers held the crack surface of the concrete. The shear strength, stiffness reduction and energy dissipation capacity of the specimens containing steel fibers were superior to those of the Vf0 specimens without steel fibers. Therefore, it is judged that the steel fiber reinforced concrete can relieve the details of the transverse reinforced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.