• Journal of the Earthquake Engineering Society of Korea
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• v.27 no.5
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• pp.203-211
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• 2023

For fast-built and safe precast concrete (PC) construction, the dry mechanical splicing method is a critical technique that enables a self-sustaining system (SSS) during construction with no temporary support and minimizes onsite jobs. However, due to limited experimental evidence, traditional wet splicing methods are still dominantly adopted in the domestic precast industry. For PC beam-column connections, the current design code requires achieving emulative connection performances and corresponding structural integrity to be comparable with typical reinforced concrete (RC) systems with monolithic connections. To this end, this study conducted the standard material tests on mechanical splices to check their satisfactory performance as the Type 2 mechanical splice specified in the ACI 318 code. Two PC beam-column connection specimens with dry mechanical splices and an RC control specimen as the special moment frame were subsequently fabricated and tested under lateral reversed cyclic loadings. Test results showed that the seismic performances of all the PC specimens were fully comparable to the RC specimen in terms of strength, stiffness, energy dissipation, drift capacity, and failure mode, and their hysteresis responses showed a mitigated pinching effect compared to the control RC specimen. The seismic performances of the PC and RC specimens were evaluated quantitatively based on the ACI 374 report, and it appeared that all the test specimens fully satisfied the seismic performance criteria as a code-compliant special moment frame system.

• Earthquakes and Structures
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• v.27 no.2
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• pp.143-154
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• 2024

Friction pendulums typically suffer from poor uplift-restraining. To improve the uplift-restraining and enhance the energy dissipation capacity, this article proposed a composite isolation device based on electromagnetic forces. The device was constructed based on a remote control system to achieve semi-active control of the composite isolation device. This article introduces the theory and design of an electromagnetic chuck-friction pendulum system (ECFPS) and derives the theoretical equation for the ECFPS based on Maxwell's electromagnetic attraction equation to construct the proposed model. By conducting 1:3 scale tests on the electromagnetic device, the gaps between the practical, theoretical, and simulation results were analyzed, and the accuracy and effectiveness of the theoretical equation for the ECFPS were investigated. The hysteresis and uplift-restraining performance of ECFPS were analyzed by adjusting the displacement amplitude, vertical load, and input current of the simulation model. The data obtained from the scale test were consistent with the theoretical and simulated data. Notably, the hysteresis area of the ECFPS was 35.11% larger than that of a conventional friction pendulum. Lastly, a six-story planar frame structure was established through SAP2000 for a time history analysis. The isolation performances of ECFPS and FPS were compared. The results revealed that, under horizontal seismic action, the horizontal seismic response of the bottom layer of the ECFPS isolation structure is greater than that of the FPS, the horizontal vibration response of the top layer of the ECFPS isolation structure is smaller than that of the FPS, and the axial force at the bottom of the columns of the ECFPS isolation structure is smaller than that of the FPS isolation structure. Therefore, the reliable uplift-restraining performance is facilitated by the electromagnetic force generated by the device.

• Journal of Energy Engineering
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• v.20 no.3
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• pp.185-190
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• 2011

This paper describes design, fabrication, and evaluation of the conduction cooled high temperature superconducting (HTS) magnet for superconducting magnetic energy storage (SMES). The HTS magnet is composed of twenty-two of double pancake coils made of 4-ply conductors that stacked two Bi-2223 multi-filamentary tapes with the reinforced brass tape. Each double pancake coil consists of two solenoid coils with an inner diameter of 500 mm, an outer diameter of 691 mm, and a height of 10 mm. The aluminum plates of 3 mm thickness were arranged between double pancake coils for the cooling of the heat due to the power dissipation in the coil. The magnet was cooled down to 5.6 K with two stage Gifford McMahon (GM) cryocoolers. The maximum temperature at the HTS magnet in discharging mode rose as the charging current increased. 1 MJ of magnetic energy was successfully stored in the HTS magnet when the charging current reached 360A without quench. In this paper, thermal and electromagnetic behaviors on the conduction cooled HTS magnet for SMES are presented and these results will be utilized in the optimal design and the stability evaluation for conduction cooled HTS magnets.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.27-36
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• 2006

Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.95-104
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• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.59-67
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• 2016

A novel instrumentation amplifier (IA) using fully-differential linear operational transconductance amplifier (FLOTA) for electronic measurement systems with low cost, wideband, and gain control with wide range is designed. The IA consists of a FLOTA, two resistor, and an operational amplifier(op-amp). The principal of the operating is that the difference of two input voltages applied into FLOTA converts into two same difference currents, and then these current drive resistor of (+) terminal and feedback resistor of op-amp to obtain output voltage. To verify operating principal of the IA, we designed the FLOTA and realized the IA used commercial op-amp LF356. Simulation results show that the FLOTA has linearity error of 0.1% and offset current of 2.1uA at input dynamic range ${\pm}3.0V$. The IA had wide gain range from -20dB to 60dB by variation of only one resistor and -3dB frequency for the 60dB was 10MHz. The proposed IA also has merits without matching of external resistor and controllable offset voltage using the other resistor. The power dissipation of the IA is 105mW at supply voltage of ${\pm}5V$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.517-526
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• 2008

A one-chip DC-DC converter circuit for OLED(Organic Light-Emitting Diode) display module of automotive clusters is newly proposed. OLED panel driving voltage circuit, which is a charge-pump type, has improved characteristics in miniaturization, low cost and EMI(Electro-Magnetic Interference) compared with DC-DC converter of PWM(Pulse Width Modulator) type. By using bulk-potential biasing circuit, charge loss due to parasitic PNP BJT formed in charge pumping, is prevented. In addition, the current dissipation in start-up circuit of band-gap reference voltage generator is reduced by 42% and the layout area of ring oscillator is reduced by using a logic voltage VLP in ring oscillator circuit using VDD supply voltage. The driving current of VDD, OLED driving voltage, is over 40mA, which is required in OLED panels. The test chip is being manufactured using $0.25{\mu}m$ high-voltage process and the layout area is $477{\mu}m{\times}653{\mu}m$.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.24 no.6
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• pp.229-236
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• 2014

A stoichiometric mixture of evaporating materials for $MnAl_2S_4$ single crystal thin films was prepared from horizontal electric furnace. To obtain the single crystal thin films, $MnAl_2S_4$ mixed crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by the Hot Wall Epitaxy (HWE) system. The source and substrate temperatures were $630^{\circ}C$ and $410^{\circ}C$, respectively. The crystalline structure of the single crystal thin films was investigated by the photoluminescence and double crystal X-ray diffraction (DCXD). The temperature dependence of the energy band gap of the $MnAl_2S_4$ obtained from the absorption spectra was well described by the Varshni's relation, $E_g(T)=3.7920eV-5.2729{\times}10^{-4}eV/K)T^2/(T+786 K)$. In order to explore the applicability as a photoconductive cell, we measured the sensitivity (${\gamma}$), the ratio of photocurrent to dark current (pc/dc), maximum allowable power dissipation (MAPD) and response time. The results indicated that the photoconductive characteristic were the best for the samples annealed in S vapour compare with in Mn, Al, air and vacuum vapour. Then we obtained the sensitivity of 0.93, the value of pc/dc of $1.10{\times}10^7$, the MAPD of 316 mW, and the rise and decay time of 14.8 ms and 12.1 ms, respectively.