• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.1299-1300
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• 2010

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.404-404
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• 2010

Despite much works have been done on the geometric structures of ripples, defects and edge atoms in a graphene device, there has been no report showing the direct correlation between the structures and the transport property. Unlike scanning tunneling microscopy or other electron microscopes, Scanning Gate Microscope (SGM) is a unique microscopic tool with which the local electronic structure and the transport property of a device can be measured simultaneously. We have performed a transport measurement in nanometer scale using a scanning gate microscope (SGM). We have found the nanoscopic pictures of electron and hole puddles and the role of graphene- device edges in the transport measurements. These experimental findings were successfully explained with a theoretical model.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.103-111
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• 2017

In this study, the thermomechanical stress and fatigue analysis of a high voltage and high current (3,300 V/1200 A) insulated gate bipolar transistor (IGBT) module used for electric locomotive applications were performed under thermal cycling condition. Especially, the reliability of the copper wire and the ribbon wire were compared with that of the conventional aluminum wire. The copper wire showed three times higher stress than the aluminum wire. The ribbon type wire showed a higher stress than the circular type wire, and the copper ribbon wire showed the highest stress. The fatigue analysis results of the chip solder connecting the chip and the direct bond copper (DBC) indicated that the crack of the solder mainly occurred at the outer edge of the solder. In case of the circular wire, cracking of the solder occurred at 35,000 thermal cycles, and the crack area in the copper wire was larger than that of the aluminum wire. On the other hand, when the ribbon wire was used, the crack area was smaller than that of the circular wire. In case of the solder existing between DBC and base plate, the crack growth rate was similar regardless of the material and shape of the wire. However, cracking occurred earlier than chip solder, and more than half of the solder was failed at 40,000 cycles. Therefore, it is expected that the reliability of the solder between DBC and base plate would be worse than the chip solder.