• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 춘계학술대회
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• pp.288-291
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• 2007

Since the residential load is an AC load and the output of solar cell is a DC power, the photovoltaic system needs the DC/AC converter to utilize solar cell. In case of driving to interact with utility line, in order to operate at unity power factor, converter must provide the sinusoidal wave current and voltage with same phase of utility line. Since output of solar cell is greatly fluctuated by insolation, it is necessary that the operation of solar cell output in the range of the vicinity of maximum power point. In this paper, DC/AC converter is three phase PWM converter with smoothing reactor. And then, feedforward control used to obtain a superior characteristic for current control and digital PLL circuit used to detect the phase of utility line.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.321-322
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• 2014

In this paper, a zero-voltage switching (ZVS) phase shift full-bridge converter is analyzed. The small-signal model is derived to design a digital controller. PLECS simulation shows how sampling method effects on transfer function of ZVS phase shift full-bridge converter.

• 전기학회논문지
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• 제58권8호
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• pp.1544-1550
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• 2009

In this paper, a new single phase voltage sag/swell compensator using direct power conversion is proposed. A new compensator consists of input/output filter, series transformer and direct ac-ac converter, which is a single-phase back-to-back PWM converter without dc-link capacitors. Advantages of the proposed compensator include: simple power circuit by eliminating dc link electrolytic capacitors and thereby, improved reliability and increased life time of the entire compensator; simple PWM strategy or compensating voltage sag/swell at the same time and reduced switching losses in the ac-ac converter. Further, the proposed scheme is able to adopt simple switch commutation method without requiring complex four-step commutation method that is commonly employed in the direct power conversion. Simulation and experimental results are shown to demonstrate the advantages of the new compensator and PWM strategy. A 220V, 3kVA single-phase compensator based on the digital signal processor controller is built and tested.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• 대한전자공학회논문지SD
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• 제42권9호
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• pp.35-40
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• 2005

본 논문에서는 1.6Gb/s에서 동작하는 digitally controlled phase-locked loop (DCPLL)를 제안한다. DCPLL은 일반적인 아날로그 PLL과 tracking analog-to-digital 변환기를 결합한 구조이다. 제안한 DCPLL에서는 tracking ADC의 출력이 voltage controlled oscillator (VCO)의 제어 전압을 생성한다. 일반적으로 사용되는 digital PLL (DPLL)은 digitally controlled oscillator (DCO)와 time-to-digit converter (TDC)로 구성된다 DCO와 TDC를 사용한 DPLL은 시간 스텝이 작을 수 록 jitter 특성이 향상되지만 전력소모는 커진다. 이 논문에서 제안한 DCPLL은 DPLL의 핵심요소인 DCO와 TDC를 사용하지 않았기 때문에 jitter, 면적, 전력소모 측면에서 유리하다. DCPLL은 $0.18\mu$m 4-metal CMOS공정을 이용하여 제작하였고 면적은 1mm $\times$0.35mm를 차지한다. 1.8V 단일 전원전압으로 정상동작에서는 59mW, power-down 모드에서는 $984\mu$W 전력을 소모하고 16.8ps rms jitter를 갖는다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.240-243
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• 2001

This paper presents the digital controller using variable gain for single-phase power factor correction (PFC) converter. Generally, the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This is why input current is distorted under low input voltage. In particular, a digital controller has more time delay than an analog controller which degrades characteristics of control loop. So, it causes the problem that the gain of current control loop isn't increased enough. In addition, the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult. In this paper, the improved digital control method for single-phase power factor converter is presented. The variable gain according to input voltage and input current help to improve current shape. The 800W converter is manufactured to verify the proposed control method.

• Journal of Power Electronics
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• 제9권3호
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• pp.410-417
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• 2009

This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권11호
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• pp.757-762
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• 2000

This paper presents a digital controller for three-phase Boost Converter. Generally, the conventional Space-Vector Pulse Width Modulation (SVPWM) have complex computation. Thereby, it should be implemented with high performance processor. In order to reduce calculation burden of the conventional SVPWM, digital controller which has a simplified SVPWM algorithm is designed in this study. A proposed digital controller consists of fuzzy pwm controller and prediction controller. In simulations and experiments, the proposed digital controller is validated.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.