• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.1-11
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• 2007

In this paper, a new fully digital control method for UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the simulation and experimental results respectively.

• Journal of Advanced Navigation Technology
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• v.24 no.6
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• pp.581-586
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• 2020

In this paper, the design process and method for a compact wideband loop antenna for terrestrial digital TV (DTV) and ultra high definition (UHD) TV applications was proposed. Horizontal slits were added on the two circular sectors of the proposed loop antenna in order to miniaturize the existing wideband loop antenna consisting of a square loop and two circular sectors. A CPW transmission line was inserted in the center of the lower circular sector as a feed line. The CPW feed line was designed using the 75 ohm port impedance for DTV and UHD TV applications, and a tapered center-signal line was designed to improve the impedance matching. The final designed antenna was fabricated on an FR4 substrate with a thickness of 0.8 mm. The experiment results show that the proposed compact loop antenna operates in the frequency band of 444.3-820.1 MHz for a VSWR < 2, which fully covers the DTV and UHD TV bands.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.91-94
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• 2000

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.277-280
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• 2001

The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25${\mu}{\textrm}{m}$ CMOS process and simulated with 2.5 V power supply.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.56-66
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• 1993

In this paper, a fuzzy logic controll(FLC) is designed for the pointing loop of the spinstabilized platform. For the fuzzy inference, a fuzzy accelerator board using the Togai InfraLogic software and digital fuzzy processor(DFP110FC) is designed, and a validation of an algorithm for fuzzy logic control is also presented. Through the simulation and the experiment, it can be seen that the designed FLC shows better performance than a conventional controller using the same loop gain.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.2
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• pp.187-196
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• 1997

This paper presents a semi-automatic methodology to synthesize executable digital controller saftware in a multi-loop control system. A digital controller is described by a task graph and end-to-end timing requirements. A task graph denotes the software structure of the controller, and the end-to-end requirements establish timing relationships between external inputs and outputs. Our approach translates the end-to-end requirements into a set of task attributes such as task periods and deadlines using nonlinear optimization techniques. Such attributes are essential for control engineers to implement control programs and schedule them in a control system with limited resources. In current engineering practice, human programmers manually derive those attributes in an ad hoc manner: they often resort to radical over-sampling to safely guarantee the given timing requirements, and thus render the resultant system poorly utilized. After task-specific attributes are derived, the tasks are scheduled on a single CPU and the compiled kernel is synthesized. We illustrate this process with a non-trivial servo motor control system.

• Journal of the Korean Solar Energy Society
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• v.27 no.2
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• pp.37-44
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• 2007

As photovoltaic(PV) power generation system becomes more common, it will be necessary to investigate islanding detection method for PV systems. Islanding of PV systems can cause a variety of problems and must be prevented. However, if the real and reactive power of the load and PV system are closely matched, islanding detection by Passive methods becomes difficult. Also, most active methods lose effectiveness when there are several PV systems feeding the same island. The active frequency drift positive feedback method(AFDPF) enables islanding detection by forcing the frequency of the voltage in the island to drift up or down. In this paper the research for the minimum value of chopping fraction gain applied digital phase-locked-loop (DPLL) to AFDPF considering output power quality and islanding prevention performance are performed by simulation and experiment according to IEEE Std 929-2000 islanding test.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.649-656
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• 2002

This paper addresses the phase noise analysis of high-speed DH-PLL(Digital Hybrid Phase-Locked Loops) frequency synthesizer. Because of the additional quantization noise of D/A converter in DH-PLL, the phase noise of DH-PLL is increased than the conventional PLL. Three kinds of noise sources such as reference input, D/A converter, and VCO(Voltage Controlled Oscillator) are considered to analyze the phase noise. It largely depends on the closed loop bandwidth and frequency synthesis division ratio(N) so that we can decide the optimal closed loop bandwidth to minimize the phase noise of DH-PLL. It is shown that the simulation results closely match with the results of analytical approach.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1489-1494
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• 2014

A hardware-in-the-loop simulation (HILS) method for a wind farm controller using a real time digital simulator (RTDS) is presented, and performance of the wind farm controller is analyzed. A 100 MW wind farm which includes 5 MW wind power generation systems (WPGS) is modeled and analyzed in RSCAD/RTDS. The wind farm controller is implemented by using a computer, which is connected to the RTDS through transmission control protocol/internet protocol (TCP/IP). The HILS results show the active power and power factor of the wind farm, which are controlled by the wind farm controller. The proposed HILS method in this paper can be effectively utilized to validate and test a wind farm controller under the environment in practice without a real wind farm.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.