• Transactions of the Korean Society of Automotive Engineers
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• v.5 no.6
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• pp.175-182
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• 1997

The purpose of this study is to investigate the effects of intake manifold shapes to improve the engine performance in a 3-cylinder LPG engine with a closed loop fuel supply system. To know the flow resistance of intake manifolds with shape, the intake negative pressure of each runner in intake manifolds were measured by using the digital pressure meter at each driving condition. And, the engine torque and power have been measured with an engine dynamometer while adjusting the optimal fuel consumption ratio with a solenoid driver. As 속 results form this experiment, the torque characteris- tics were more improved with the plenum chamber(B type intake manifold) than with the banana type(A type intake manifold). The torque characteristics were improved at mid-engine speed(rpm) range as the inner diameter of the intake manifold became smaller. And also the optimum volume among the examined plenum chamber volume was 0.74 times(590cc) the displacement of the test engine.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1538-1545
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• 1998

System reliability has been a major concern since the beginning age of the electronic digital computers. One of the modest ways of increasing reliability is to design fault-tolerant system. This paper propose a construction mechanism of fault-tolerant system for the general graph topology. This system has several spare nodes. Up to date, fault-tolerant system design is applied only to loop and tree networks. But they are very limited cases. New algorithm of this paper tried to have a capability which can be applied to any kinds of topologies without such a many restriction. the algorithm consist of several steps : minimal diameter spaning tree extraction step, optimal node decision step, original connectivity restoration step and finally redundancy graph construction step.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.1
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• pp.42-47
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• 1999

This paper presents the information transmission between on-board and ground-site in MAGLEV. considering safety and high speed operation and density operation, information transmission between them is necessary. Therefore it is necessary for transmission system to ensure high speed transmission, low error rate, massive information, and reliability of information. To provide above conditions, 1.1km signal line assembly was constructed and Frequency Shift Keying(FSK) modulation and Open System Interconnection(OSI) based high-level data link control(HDLC) protocol are applied. To modulate digital signal for transmission from ground-site to on-board, carrier frequency of 70kHz is used and 90khz is used for transmission from on-board to ground-site. Transmission speed is 2400bps for consideration of train speed, quantity of information, and data error rate. And this paper introduces information monitoring considering user interface and presents the method for an effective data transmission in MAGLEV which is now being tested and intends to provide for an intelligent train operation system in future.

• Nuclear Engineering and Technology
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• v.27 no.5
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• pp.730-742
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• 1995

The steam generator feedwater and level control system is designed by two steps of the feedwater control design and the feedback loop controller design. The feedwater sen system is designed by the optimal LQR/LQG approach and then is modified by the LTR method to recover the robustness. The plant characteristics are subject to change with the power variation and these dynamic properties are considered in the design of the feedback controller. All the designs are made in the continuous domain and are digitalized by applying the proper sampling period. The system is simulated for the two cases of power increase and decrease. From the results of simulation, it is found that the controller constants would rather be invariable during the power increase, while for the case of power decrease they should be changed with the power variation to keep the system stability.

• Journal of the Korean Institute of Intelligent Systems
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• v.21 no.5
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• pp.595-601
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• 2011

This paper presents balancing control of inverted pendulum on the ROBOKER arm using visual information. The angle of the inverted pendulum placed on the robot arm is detected by a stereo camera and the detected angle is used as a feedback and tracking error for the controller. Thus, the overall closed loop forms a visual servoing control task. To improve control performance, neural network is introduced to compensate for uncertainties. The learning algorithm of radial basis function(RBF) network is performed by the digital signal controller which is designed to calculate floating format data and embedded on a field programmable gate array(FPGA) chip. Experimental studies are conducted to confirm the performance of the overall system implementation.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.238-246
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• 2011

A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.350-353
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• 2013

In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.7
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• pp.1289-1294
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• 2010

In this paper, a new discrete integral static output feedback variable structure controller based on the a new integral dynamic-type sliding surface and output feedback discrete version of the disturbance observer is suggested for the control of uncertain linear systems. The reaching phase is completely removed by introducing a new proposed integral dynamic-type sliding surface. The output feedback discrete version of disturbance observer is presented for effective compensation of uncertainties and disturbance. A corresponding control with disturbance compensation is selected to guarantee the quasi sliding mode on the predetermined integral dynamic-type sliding surface for guaranteeing the designed output in the integral dynamic-type sliding surface from any initial condition for all the parameter variations and disturbances. Using discrete Lyapunov function, the closed loop stability and the existence condition of the quasi sliding mode is proved. Finally, an illustrative example is presented to show the effectiveness of the algorithm.

• Journal of Power Electronics
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• v.3 no.3
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• pp.185-196
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• 2003

In this paper, the single-phase static VAR compensator (SVC) is applied to regulate and stabilize the generated terminal voltage of the single-phase self-excited induction generator (single-phase SEIG) driven by a variable-speed prime mover (VSPM) under the conditions of the independent inductive load variations and the prime mover speed changes The conventional fixed gain PI controller-based feedback control scheme is employed to adjust the equivalent capacitance of the single-phase SVC composed of the fixed excitation capacitor FC in parallel with the thyristor switched capacitor TSC and the thyristor controlled reactor TCR The feedback closed-loop terminal voltage responses in the single-phase SEIG coupled by a VSPM with different inductive passive load disturbances using the single-phase SVC with the PI controller are considered and discussed herem. A VSPM coupled the single-phase SEIG prototype setup is established. Its experimental results are illustrated as compared with its simulation ones and give good agreements with the digital simulation results for the single-phase SEIG driven by a VSPM, which is based on the SVC voltage regulation feedback control scheme.