• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.10
• /
• pp.1845-1851
• /
• 2016

In this paper, a design method for a wideband square loop antenna for Digital TV applications is studied. The proposed loop antenna is a square loop antenna combined with circular sectors to connect with central feed points. The square loop is used instead of the circular loop in order to miniaturize the antenna size. The input reflection coefficient and gain characteristics of the proposed antenna are analyzed to match with the 75 ohm port impedance for DTV applications. The effects of the gap between the circular sectors and the length of the square loop on the input reflection coefficient and gain characteristics are examined to obtain the optimal design parameters. The optimized antenna is fabricated on an FR4 substrate, and the experiment results show that it operates in the frequency band of 470-1,300 MHz for a VSWR < 2, which assures the operation in the DTV band.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.4
• /
• pp.506-517
• /
• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Information and Communications Magazine
• /
• v.3 no.1
• /
• pp.52-63
• /
• 1986

This paper discusses the network evolution strategies, worldwide trends in fiber optics systems, fiber hub in KTA access network, positioning the access network for new digital services - DLC(Digital Loop Carrier), CSA(Carrier Serving Area), and fiber optics systems overlay in the existing access network and its evolution toward near term ISDN.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.2
• /
• pp.46-52
• /
• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.12 s.91
• /
• pp.1161-1167
• /
• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.39 no.1
• /
• pp.56-62
• /
• 2011

A Satellite transponder is mounted on the Satellite and performs radio communications with the ground station. A Digital transponder compared to The analog transponder is made easy and accurate performance prediction. Also Modulation Scheme, Data Rate, Loop Bandwidth, Modulation Index and etc. can be changed on orbit, by implementing FPGA can reduce the weight and volume. The core technology of digital transponder is Carrier Recovery loop. Dynamic Range, Frequency Tracking Range, Frequency Tracking Rate and Coherent performance are determined by the performance of the Carrier Recovery loop. In this paper, we proposed the structure of Carrier Recovery loop for the Satellite digital transponder, then tested and verified the structure.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.11
• /
• pp.1-10
• /
• 1993

A Study on New Digital In this paper, we propose a new Angular Form Carrier Recovery Loop(AFCR loop) for PSK modulation technique. AF CR loop includes detected angle symbol and Multi Level Hardlimiter. Using zero crossing DPLL, we model 1st 2nd AF CR loop, and also derive SCurve. In order to prove steady state operation of AF CR loop, we evaluate performance of this loop by Monte-Carlo and analytical simulation method. We also compare the performance of AF CR loop to that of other loop in terms of acquisition, S-Curve, and RMS jitter. From the comparison result, we verify that the performance of AF CR loop operates well in steady state.

• Proceedings of the KIPE Conference
• /
• 2011.07a
• /
• pp.87-88
• /
• 2011

본 논문은 최근 빠른 속도로 성장하고 있는 신재생에너지 분야 중 태양광을 이용한 계통연계형 PV PCS의 PLL(Phase Locked Loop) 기법을 DSP로 처리할 수 있도록 디지털 논리회로로 구현하는 DPLL(Digital Phase Locked Loop) 기법을 제시하고 모델링과 시뮬레이션을 통하여 검증한다.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.3 s.96
• /
• pp.154-163
• /
• 1999

In this paper, an ultra precision positioning system has been developed using dual servo loop control. For positioning system having long distance with ultra precision , the combination of global stage and micro stage was required. A servo motor based ball screw is used as a global stage and the piezo actuator as a micro stage. For the improvement of positional precision, the digital Chebyshev filter is implemented in the developed to dual servo system. Therefore, the positional repeatability has been achieved within ${\pm}$ 10 mm, and this technique can be applied to develop precision semiconductor equipments such as lithography steppers and probers.

• ETRI Journal
• /
• v.33 no.3
• /
• pp.366-373
• /
• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.