• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.12
• /
• pp.1287-1296
• /
• 2009

It is very important to estimate the Signal to Noise Ratio(SNR) of received signal in time varying channel state. Most SNR estimation techniques derive the SNR estimates solely from the samples of the received signal after the matched filter. In the severe distorted wireless channel, the performance of these estimators become unstable and degraded. LP-based SNR estimator which can operate on data samples collected at the front-end of a receiver shows more stable performance than other SNR estimator. In this paper, we study an efficient SNR estimation algorithm based on LP and propose a new estimation method to decrease the computation complexity. Proposed algorithm accomplishes the SNR estimation process efficiently because it uses the forward prediction error and its conjugate value during the linear prediction error update. Via the computer simulation, the performance of this proposed estimation method is compared and discussed with other conventional SNR estimators in digital communication channels.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.129-140
• /
• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• Journal of information and communication convergence engineering
• /
• v.4 no.4
• /
• pp.170-173
• /
• 2006

Recently, with increasing efficiency of DSC (photo-electrochemical using a nano-particle), The Performance of DSC solar generation system also needs improvement. The approach consists of a Fly-back DC-DC (transfer ratio 1:10) converter to boost the DSC cell voltage to 300VDC. The four switch (MOSFET) inverter is employed to produce 220V, 60Hz AC outputs. High performance, easy manufacturability, lower component count., safety and cost are addressed. Protection and diagnostic features form an important part of the design. Another highlight of the proposed design is the control strategy, which allows the inverter to adapt to the: requirements of the load as well as the power source. A unique aspect of the design is the use of the DSP TMS320LF2406 to control the inverter by current and voltage feed-back. Efficient and smooth control of the: power drawn from the DSC Cell is achieved by controlling the front end DC-DC converter in current mode.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2004.11a
• /
• pp.103-106
• /
• 2004

본 논문에서는 PC 기반 지상파 DMB(Terrestrial Digital Multimedia Broadcasting, T-DMB) 수신기를 위한 SW 최적화에 대해 설명한다. 이 수신기는 PC 외부에 지상파 DMB 신호를 안테나로 수신하여 복조하고 채널 복호하는 프론트 엔드(front-end) 수신 모듈을 이용, USB를 통하여 RS(Reed-Solomon) 부호화된 MPEG-2 TS(Transport Stream) 데이터를 읽어 들여 RS 복호, TS 역다중화, 비디오 복호, 오디오 복호 등의 SW 처리 과정을 거쳐 디스플레이 상에 수신 내용을 표시하게 된다. 본 논문에서는 저사양 PC에서도 T-DMB를 수신할 수 있도록 H.264/MPEG-4 AVC(Advanced Video Coding) 복호 과정을 최적화한 결과에 대해 설명한다.

• Proceedings of the IEEK Conference
• /
• 2001.06e
• /
• pp.25-28
• /
• 2001

This paper introduce a millimeter-wave radar system. As Fig 1 shows, This system consists of millimeter-wave radar front-end and digital signal processing parts through receive waves regarding up-coming obstacles. The system works as follow process; (1) Generate regular tripodal waves using the FMCW pulse generator (2) Transmit/Receive waves regarding up-coming obstacles (3) Analog filtering (4) FIFO memory interface (5) FFT(Fast Fourier Transform) (6) Calculation of distance / speed between cars (7) Object display and calibration. We have progress to solve the problem like as increase of traffic accidents causing damage and injuries due to the increased number of motor vehicles and long distance driving, and Need for a device to help drivers who are in trouble due to bad weather conditions. We are expect to Take the lead as a core technology in the ITS industry and to develop circuit and signal processing technologies related to millimeter-wave bandwidth.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.6
• /
• pp.37-43
• /
• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2004.05a
• /
• pp.412-418
• /
• 2004

In this paper, a new distributed intelligent control module based on LonWorks fieldbus for air handling unit(AHU) of heating, ventilating and air-conditioning(HVAC) is proposed to replace with a conventional direct digital control(DDC) with 32 bit microprocessor. This article also addresses an Internet-based HVAC system architecture that combines Web technology and networking. The proposed control architecture has a excellent features such as highly compact and flexible function design, a low priced smart front-end and reliable performance with various functions. This also addresses issues in control network configuration, logical design of field devices by S/W tool, Internet networking and electronic element installation. Experimental results showing the system performance are also included in this paper.

• Information and Communications Magazine
• /
• v.14 no.3
• /
• pp.75-86
• /
• 1997

This manuscript describes the high level system design for the DCP system. The DCP HS and BS transceivers are composed of five systems, including the RF/IF unit, the Analog Front End(AFE), the baseband modem, the voice codec and the micro-controller. In the following, the core transceiver architecture with the primary functions at these subsystem is described.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2003.11a
• /
• pp.251-257
• /
• 2003

In this paper, a new distributed intelligent control module based on LonWorks fieldbus for air handling unit(AHU) of heating, ventilating and air-conditioning(HVAC) is proposed to replace with a conventional direct digital control(DDC) with 32 bit microprocessor. The proposed control architecture has a excellent features such as highly compact and flexible function design, a low priced smart front-end and reliable performance with various functions. This also addresses issues in control network configuration, logical design of field devices by S/W tool, Internet networking and electronic element installation. Experimental results showing the system performance are also included in this paper.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.16 no.6
• /
• pp.253-258
• /
• 2021

In this paper, we developed a hardware and software platform of the real-time data logging system to verify radar FEM (Front-end Module) and signal-processing algorithms. We developed a hardware platform based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and implemented firmware software to verify the various FEMs. Moreover, we designed PC based software platform to control radar logging parameters and save radar data. The developed platform was verified using 24 GHz multiple channel FMCW (Frequency Modulated Continuous Wave) in an environment of stationary and moving targets of chamber room.