• Proceedings of the Korean Society of Computer Information Conference
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• 2018.01a
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• pp.31-34
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• 2018

We live in the digital era, and the characteristics of our customers in the digital era are constantly changing. That's why understanding business requirements and converting them to technical requirements is essential, and you have to understand the data model behind the business layout. Moreover, BI(Business Intelligence) is at the crux of revolutionizing enterprise to minimize losses and maximize profits. In this paper, we have described a leading study about the situation of desk-top BI(software product & programming language) in aspect of front-end side and the Data Lake platform based on Big Data by data modeling in aspect of back-end side to support the business intelligence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.114-121
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• 2005

In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.5 no.2
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• pp.61-67
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• 2012

In this paper, In this paper, we consider a dynamic range in the frequency converter to obtain a high conversion gain and linearity while operating area proposed to broaden the design. Super-heterodyne RF Front-End style was applied to the active mixer stage, GaAs devices were used. Circuit design easy and simple forms benefit circuit is constructed in the drain mixer, passive mixer with the operating area were compared and analyzed. The simulation results of the conversion gain of 2.4dB and 0.2dBm about a gain-compression point, and showed the dynamic range of 71.9dB, when compared with passive mixers, dynamic range of approximately 6dB improvement was identified. Measurements of an approximately 2dB conversion gain and-1.0dBm of the gain-compression point, and confirmed that the active area of 71.1dB. When compared with passive mixers, dynamic range of is reduced by approximately 8dB has been improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.638-646
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• 2005

In recent wireless communications, direct conversion transceiver or If sampling SDR-based receivers have being designed as an alternative to conventional transceiver topologies. In direct conversion receiver a.chitectu.e, the 1.equency/phase offset between the RF input signal and the local oscillator signal is a major impairment factor even though the conventional AFC/APC compensates the service deterioration due to the offset. To rover the limited tracking range of the conventional method and effectively aid compensation scheme in terms of I/Q channel imbalances, the frequency/phase offset compensation in RF-front end signal stage is proposed in this paper. In RF-front end, the varying phase offset besides the fixed large frequency/phase offset are corrected by using early-late phase compensator. A more simple frequency and phase tacking function in digital signal processing stage of direct conversion receiver is effectively available by an ingenious frequency/phase offset tracking method in RF front-end stage.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.209-212
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• 2003

본 논문에서는 PC 환경에서 지상파 디지털 멀티미디어 방송(Digital Multimedia Broadcasting, DMB)을 수신할 수 있는 PC 기반 지상파 DMB 수신기용 백엔드 시스템 개발에 대해 서술한다. 지상파 DMB는 기존의 지상파 아날로그 또는 디지털 TV에 비해 탁월한 이동 수신 성능을 보인다. 본 논문에서는 국내 지상파 DMB 표준안에 부합하는 수신기의 백엔드 (back-end)를 PC 환경에서 소프트웨어로 구현하였다. 지상파 DMB는 유럽의 디지털 오디오 방송(Digital Audio Broadcasting, DAB) 표준인 EUREKA-147을 기반으로 MPEG-4 표준에 의한 멀티미디어 서비스를 제공한다. 지상파 DMB의 멀티미디어 서비스는 MPEG-4 AVC(Advance Video Coding) 압축 비디오와 BSAC(Bit Slice Arithmetic Coding) 압축 오디오를 MPEG-4 시스템의 SL(Sync Layer) 표준으로 패킷화 후 MPEG-2 TS(Transport Stream)에 실어 DAB의 스티림 모드를 통해 전송하는 방식을 사용한다. 본 논문에서는, 지상파 DMB 수신을 위한 프론트엔드(front-end)는 외장형 기기를 이용하고, 이로부터 USB 인터페이스를 통해 기저대역 다중화 스트림을 PC 상으로 업로드한 뒤, 소프트웨어에 의해 역다중화하고 압축을 푼 후, 오디오와 비디오를 재생하는 지상파 DMB 백엔드 시스템을 구현하고 이를 검증하였다.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1346-1349
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• 2002

This paper presents the design and implementation of 16-QAM modem that can be applied to fixed broadband wireless access systenm. It is implemented in the hardware prototype that consist of FPGA(Field Programmable Gate Array) for digital signal processing and analog front end module for analog signal processing. We provide 20.48Mbps data rate using implemented modem and test the modem in KOREA 26㎓ broadband wireless local loop system including IFU(Intermediate Frequency Unit) and RFU(Radio Frequency Unit) via air interface.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.579-587
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• 2014

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.182-192
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• 2015

This study develops a digital control scheme with power factor correction for a front-end converter in an electric vehicle battery charger. The front-end converter acts as the boost-type switching-mode rectifier. The converter assumes the two roles of the battery charger, which include power factor control and robust charging performance. The proposed control scheme consists of a charging control algorithm and a grid current control algorithm. The scheme aims to obtain unity input power factor and robust performance. Based on the linear average model of the converter, a constant-current constant-voltage charging control algorithm that passes through only one proportional-integral controller and a current feed-forward path is proposed. In the current control algorithm, we utilized a second band pass filter, a single-phase phase-locked loop technique, and a duty-ratio feed-forward term to control the grid current to be in phase with the grid voltage and achieve pure sinusoidal waveform. Simulations and experiments were conducted to verify the effectiveness of the proposed control scheme, both simulations and experiments.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.8
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• pp.3103-3120
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• 2015

This paper presents a single-phase energy metering chip with built-in calibration function to measure electric power quantities. The entire chip consists of an analog front end, a filter block, a computation engine, a calibration engine, and an external interface block. The key design issues are how to reduce the implementation costs of the computation engine from repeatedly used arithmetic operations and how to simplify calibration procedure and reduce calibration time. The proposed energy metering chip simplifies the computation engine using time-division multiplexed arithmetic units. It also provides a simple and fast calibration scheme by using integrated digital calibration functionality. The chip is fabricated with 0.18-μm six-layer metal CMOS process and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4096 kHz and consumes 9.84 mW in 3.3 V supply.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.258-264
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• 2015

The first 77 GHz transceiver that applies a heterodyne structure-based linear frequency modulation-frequency shift keying (LFM-FSK) front-end module (FEM) is presented. An LFM-FSK waveform generator is proposed for the transceiver design to avoid ghost target detection in a multi-target environment. This FEM consists of three parts: a frequency synthesizer, a 77 GHz up/down converter, and a baseband block. The purpose of the FEM is to make an appropriate beat frequency, which will be the key to solving problems in the digital signal processor (DSP). This paper mainly focuses on the most challenging tasks, including generating and conveying the correct transmission waveform in the 77 GHz frequency band to the DSP. A synthesizer test confirmed that the developed module for the signal generator of the LFM-FSK can produce an adequate transmission signal. Additionally, a loop back test confirmed that the output frequency of this module works well. This development will contribute to future progress in integrating a radar module for multi-target detection. By using the LFM-FSK waveform method, this radar transceiver is expected to provide multi-target detection, in contrast to the existing method.