• Title/Summary/Keyword: Digital error correction

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Equalization Digital On-Channel Repeater for Single Frequency Network Composition of ATSC Terrestrial Digital TV Broadcasting (ATSC 지상파 디지털 TV 방송의 단일 주파수 망 구성을 위한 등화형 디지털 동일 채널 중계기)

  • Park Sung Ik;Eum Homin;Lee Yong-Tae;Kim Heung Mook;Seo Jae Hyun;Kim Hyoung-Nam;Kim Seung Won
    • Journal of Broadcast Engineering
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    • v.9 no.4 s.25
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    • pp.371-383
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    • 2004
  • In this paper we consider technological requirements to broadcast digital television signals using single frequency networks (SFN) in the Advanced Television Systems Committee (ATSC) transmission systems and propose equalization digital on-channel repeater (EDOCR) that overcomes the limitations of conventional digital on-channel repeaters (DOCRs). Since there are no forward error correction (FEC) decoder and encoder, the EDOCR does not have an ambiguity problem. In addition, since an adaptive equalizer in the EDOCR removes multi-path signals, additive white Gaussian noise (A WGN), and feedback signal due to low antenna isolation, the EDOCR may have good output signal quality with high power.

Digital correction and calibration circuits for a high-resolution CMOS pipelined A/D converter (파이프라인 구조를 가진 고해상도 CMOS A/D 변환기를 위한 디지탈 교정 및 보정 회로)

  • 조준호;최희철;이승훈
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.6
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    • pp.230-238
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    • 1996
  • In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

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A Study on Improved Model of Digital Basemap Database (수치지도 자료기반구축 개선모형에 관한 연구)

  • 유복모;신동빈
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.17 no.3
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    • pp.213-223
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    • 1999
  • This study provides a improved model of digital basemap production that can efficiently identify and correct the various errors generated in digital map production process. In order to fulfill the requirements that the new model calls for, this study provides a typology of errors by analyzing the errors in digital basemap data. Computer programs for automatic error searching and for checking the correctness of the digital codes in the data have also been developed. Exsiting visual error-checking process has also been analyzed and more systematic process is suggested. As a result, it is found that the improved model of digital basemap production suggested in this study contributes to improving the quality of the digital map database by providing a systematic method for efficient error-searching and correction of digital map data.

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Estimation of Error Performance for Digital Satellite Communication (디지털 위성통신 시스템에서의 오류 성능 추정)

  • Yeo, Sung-Moon;Kim, Soo-Young
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.2
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    • pp.52-59
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    • 2008
  • Recommendation ITU-R S.1062 specifies the performance of digital satellite systems. The performance objectives were given in terms of bit error probability divided by the average number of errors per burst versus percentage of time. This performance objective is highly dependent on the forward error correction(FEC) coding schemes used in the system. This implies that we need an effective way of estimating the error performance of a system by the given FEC scheme. In this paper, we derive theoretical formula to estimate performance measure of digital satellite systems defined in Recommendation ITU-R S.1062. We demonstrate various estimation results, and verify them by comparing to the simulation results.

Mixed-Domain Adaptive Blind Correction of High-Resolution Time-Interleaved ADCs

  • Seo, Munkyo;Nam, Eunsoo;Rodwell, Mark
    • ETRI Journal
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    • v.36 no.6
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    • pp.894-904
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    • 2014
  • Blind mismatch correction of time-interleaved analog-to-digital converters (TI-ADC) is a challenging task. We present a practical blind calibration technique for low-computation, low-complexity, and high-resolution applications. Its key features are: dramatically reduced computation; simple hardware; guaranteed parameter convergence with an arbitrary number of TI-ADC channels and most real-life input signals, with no bandwidth limitation; multiple Nyquist zone operation; and mixed-domain error correction. The proposed technique is experimentally verified by an M = 4 400 MSPS TI-ADC system. In a single-tone test, the proposed practical blind calibration technique suppressed mismatch spurs by 70 dB to 90 dB below the signal tone across the first two Nyquist zones (10 MHz to 390 MHz). A wideband signal test also confirms the proposed technique.

A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance

  • Eo, Ji-Hun;Kim, Sang-Hun;Kim, Mun-Gyu;Jang, Young-Chan
    • Journal of information and communication convergence engineering
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    • v.10 no.1
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    • pp.85-90
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    • 2012
  • A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

Georegistration of Airborne LiDAR Data Using a Digital Topographic Map (수치지형도를 이용한 항공라이다 데이터의 기하보정)

  • Han, Dong-Yeob;Yu, Ki-Yun;Kim, Yong-Il
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.30 no.3
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    • pp.323-332
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    • 2012
  • An airborne LiDAR system performs several observations on flight routes to collect data of targeted regions accompanying with discrepancies between the collected data strips of adjacent routes. This paper aims to present an automatic error correction technique using modified ICP as a way to remove relative errors from the observed data of strip data between flight routes and to make absolute correction to the control data. A control point data from the existing digital topographic map were created and the modified ICP algorithm was applied to perform the absolute automated correction on the relatively adjusted airborne LiDAR data. Through such process we were able to improve the absolute accuracy between strips within the average point distance of airborne LiDAR data and verified the possibility of automation in the geometric corrections using a large scale digital map.

Development of Data/Video Transmission System for flying vehicle (비행체 탑재용 데이터/영상 복합전송장치 개발)

  • Cho, Dong-Sik;Ra, Sung-Woong
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.35 no.11
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    • pp.1052-1057
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    • 2007
  • A highly reliable Video Transmission System (VTS) was developed in order to obtain both video and digital data simultaneously in the real time flight test situation of a flying vehicle. The VTS integrates GPS data, digital telemetry data and video signals into a compact digital data package which is compressed and processed by an MPEG-2 Encoder and a DVB-S modulator respectively. The DVB-S modulator is composed of a specially devised Forward Error Correction processor and base band QPSK modulator. The designed VTS was verified and proved for its required functioning and performance through separate flight tests using an airplane and missiles.

Development of Video Transmission System for Rocket (로켓 탑재를 위한 영상 송수신장치 개발)

  • Cho, Dong-Sik;Rha, Sung-Woong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.2
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    • pp.60-65
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    • 2009
  • A highly reliable Video Transmission System (VTS) was developed in order to obtain both video and digital data simultaneously in the real time flight test situation of a flying vehicle. The VTS integrates GPS date digital telemetry data and video signals into a compact digital data package which is compressed and processed by an MPEG-2 Encoder and a modulator respectively. The modulator is composed of a specially devised Forward Error Correction processor and base band QPSK modulator. The designed VTS was verified and proved for its required functioning and performance through separate flight tests using an airplane and Rockets.

Updating Digital Map using Images from Airborne Digital Camera (항공디지털카메라 영상을 이용한 수치지도 갱신)

  • Hwang, Won-Soon;Kim, Kam-Rae
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.25 no.6_2
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    • pp.635-643
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    • 2007
  • As the availability of images from Airborne Digital Camera with high resolution is expanded, a lot of concern are in the production and update of digital map. This study presents the method of updating the digital map at the scale of 1/1,000 using images from Aerial Digital Camera. Geometric correction was completed using GPS surveying data. For digital mapping, digital photogrammetric system was utilized to digitize buildings and roads. The absolute positional accuracy was evaluated using GPS surveying data and the relative positional accuracy was evaluated using the digital map produced by analytical mapping. The absolute positional accuracy was as follows: RMSE in X and Y were ${\pm}0.172m\;and\;{\pm}0.127m$, and average distance error was 0.208m. The relative positional accuracy was as follows: RMSE in X and Y were ${\pm}0.238m\;and\;{\pm}0.281m$, and average distance error was 0.337m. Accuracies of updating digital map using images from airborne Digital Camera were within allowable error established by NGII. Consequently, images from airborne Digital Camera can be used in various fields including the production of the national basic map and the GIS of local government.