• 대한전기학회논문지:전기기기및에너지변환시스템부문B
• /
• 제53권6호
• /
• pp.380-387
• /
• 2004

In accordance with the computerization of railway signaling systems, the interface link between the signaling systems has been replaced by a digital communication channel. At the same time, the importance of the communication link has become increasingly significant. However, there are some questionable matters in the current state of railway signaling systems in KNR. First, different communication protocols have been applied to create an interface between railway signaling systems although the protocols have the same functions. Next, the communication protocols currently used in the railway fields have some illogical parts such as structure, byte formation, error correction scheme, and so on. To solve these matters, the standard communication protocol for railway signaling systems is designed. The newly designed protocol is overviews in this paper. And the simulation is performed to analysis the performance of data link control for designed protocol. According to this simulation, it is identified that the link throughput of new protocol is improved about 10% and the frame error rate is improved than existing protocol. And it is verified the safety and liveness properties of designed protocol by using a formal method for specifying the designed protocol. It is expected that there will be an increase in safety, reliability and efficiency in terms of the maintenance of the signaling systems by using the designed communication protocol for railway signaling.

• Journal of the Optical Society of Korea
• /
• 제6권4호
• /
• pp.172-179
• /
• 2002

Like the conventional digital storage systems, volume holographic memory can be deteriorated by burst errors due to its high-density storage characteristics. These burst errors are used byoptical defects such as scratches, dust particles, etc. and are two-dimensional in a data page. To deal with these errors, we introduce some concepts for describing them and propose efficient two- dimensional interleaving schemes. The schemes are two-dimensional lattices of an error-correction code word and have equilateral triangular and square structures. Using these structures, we can minimize the number of code words that are interleaved and improve the efficiency of the system. For large size burst errors, the efficient interleaving structure is an equilateral triangular lattice. However, for some small size burst errors, it is reduced to a square lattice.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1998년도 추계종합학술대회 논문집
• /
• pp.715-718
• /
• 1998

본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.

• International Journal of Contents
• /
• 제9권1호
• /
• pp.33-37
• /
• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
• /
• pp.375-377
• /
• 2006

A Analog parallel processing-based Viterbi decoder which decodes PRML signal of DVD has been designed by CMOS circuit. The analog processing-based Viterbi decoder implements are functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The Analog parallel processing-based Viterbi decoding technology is applied for the PR(1,2,2,1) signal decoding of DVD. The benefits are low power consumption and less silicon consumption. In this paper, the comparison of the Analog parallel processing-based Viterbi Decoder which has a function of the error correction between Max operation and Average operation is discussed.

• 전자공학회논문지S
• /
• 제34S권11호
• /
• pp.16-24
• /
• 1997

In order to prevent the presence of the residual phase difference at the discriminator output by the existing AFC techniques, we propose a new automatic frequency control(AFC) tracking algorithm for QPSK demodulation at the digital direct broadcasting satellite(DBS) receiver, which we call a rotational decision-directed AFC(RDDAFC). The RDDAFC rotates the decision boundary for the kth received symbol by the frequency deterctor output of the (k-1)th received symbol. Tracking performances of carrier frequency offset by the proposed RDDAFC algorithm are evaluated through computer simulations under the practical DBS channel conditions with a carrier frequency offset of 2.3MHz when S/N equals 2dB. Test results show that the total pull-in time of the RDDAFC is 1.697msec for 10$^{-3}$ SER before forwared error correction at the receiver.

• 한국철도학회:학술대회논문집
• /
• 한국철도학회 2010년도 춘계학술대회 논문집
• /
• pp.1075-1080
• /
• 2010

There have been lots of researches for High Performance Digital Signal Processing performance enhancement on a GPU(Graphic Processor Unit). These kinds of parallelizing can enable massive signal processing, so we can have advantage's of processing various of signal processing standards with GPU. In this paper we introduce Low Density Parity Check(LDPC) which is one of the Foward Error Correction(FEC). And we have achieved computational time reduce by using CUDA as a parallelizing scheme.

• 정보통신설비학회논문지
• /
• 제8권4호
• /
• pp.207-215
• /
• 2009

In recent digital communication systems, the performance of Turbo Code used as the error correction coding method depends on the interleaver size influencing the free distance determination and iterative decoding algorithms of the turbo decoder. However, some iterations are needed to get a better performance, but these processes require large time delay. Recently, methods of reducing the number of iteration have been studied without degrading original performance. In this paper, the new method combining ME (Mean Estimate) stopping criterion with SDR (sign difference ratio) stopping criterion of previous stopping criteria is proposed, and the fact of compensating each method's missed detection is verified Faster decoding realizes that reducing the number of iterative decoding about 1~2 times by adopting our proposed method into serially concatenation of both decoder. System Environments were assumed DS-CDMA forward link system with intense MAI (multiple access interference).

• 대한원격탐사학회:학술대회논문집
• /
• 대한원격탐사학회 2009년도 춘계학술대회 논문집
• /
• pp.270-274
• /
• 2009

한반도의 정밀관측을 목적으로 개발된 KOMPSAT-2위성의 영상을 활용하기 위해서는 촬영 시 발생하는 기하학적 왜곡의 보정이 필요하다. 본 연구에서는 지상기준점(Ground Control Point: GCP) 선택의 세 가지 특성을 각각 적용하여 기하보정을 하였다. 보정 영상의 정확도 검정을 위하여 수치지도(digital map)를 이용한 평균제곱근오차(Root Mean Square Error: RMSE)와 육안검사를 통해 정확도를 비교하였다. 그 결과 영상의 중앙은 선형 교차점을 선택한 방법이 가장 정확하였고, 가장자리는 건물의 모서리 또는 건물의 중심을 선택한 방법이 우수하였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1999년도 하계학술대회 논문집 G
• /
• pp.3199-3201
• /
• 1999

Convolutional coding with Viterbi decoding is known as a powerful method for forward error correction among many kinds of channel coding methods. This paper presents a soft decision Viterbi decoder which has systolic array trace-back architecture[1]. Soft decision is known as more effective method than hard decision and most of digital communication systems use soft decision. The advantage of using a systolic array decoder is that the trace-back operation can be accomplished continuously in an array of registers in a pipe-line fashion, instead of waiting for the entire trace-back procedure to be completed at each iteration. Therefore it may be suitable for faster communication system. We described operations of each module of the decoder and showed results of the logic synthesis and functional simulation.