• Title/Summary/Keyword: Digital distortion

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Efficient Hybrid Carrier Based Space Vector Modulation for a Cascaded Multilevel Inverter

  • Govindaraju, C.;Baskaran, K.
    • Journal of Power Electronics
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    • v.10 no.3
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    • pp.277-284
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    • 2010
  • This paper presents a novel hybrid carrier based space vector modulation for cascaded multilevel inverters. The proposed technique inherits the properties of carrier based space vector modulation and the fundamental frequency modulation strategy. The main characteristic of this modulation are the reduction of power loss, and improved harmonic performance. The carrier based space vector modulation algorithm is implemented with a TMS320F2407 digital signal processor. A Xilinx Complex Programmable Logic Device is used to develop the hybrid PWM control algorithm and it is integrated with a digital signal processor for hybrid carrier based space vector PWM generation. The inverter offers less weighted total harmonic distortion and it operates with equal electrostatic and electromagnetic stress among the power devices. The feasibility of the proposed technique is verified by spectral analysis, simulation, and experimental results.

A Compensation of Linear Distortion for Loudspeaker Using the Adaptive Digital Filter (적응 디지탈 필터를 이용한 확성용 스피커의 선형 왜곡 보상)

  • 전희영;차일환
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 1995.06a
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    • pp.165-170
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    • 1995
  • In this paper, it is attempted to apply the adaptive digital signal processing to compensate for a linear distortion of a loudspeaker and implement a real time hardware for that purpose. The real time system is implemented by using the DSP56001, a general purpose signal processor, as a host processor and the DSP56200, a cascadable adaptive FIR filter peripheral chip, as an adaptive digital filter. The system has 1000 taps at a 44.1kHz. After inverse modeling of under_compensation_speaker, the system reduces loudspeaker's linear distortions by pre-processing an input audio signal to loudspeaker. The experiment shows satisfactory results; after adaption with white noise as input signal for 60sec, the flat amplitude and linear phase frequency characteristics is found to lie over a wide frequency range of 100Hz to 20kHz.

Feasibility of Using an Automatic Lens Distortion Correction (ALDC) Camera in a Photogrammetric UAV System

  • Jeong, Hohyun;Ahn, Hoyong;Park, Jinwoo;Kim, Hyungwoo;Kim, Sangseok;Lee, Yangwon;Choi, Chuluong
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.33 no.6
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    • pp.475-483
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    • 2015
  • This study examined the feasibility of using an automatic lens distortion correction (ALDC) camera as the payload for a photogrammetric unmanned aerial vehicle (UAV) system. First, lens distortion for the interior orientation (IO) parameters was estimated. Although previous studies have largely ignored decentering distortion, this study revealed that more than 50% of the distortion of the ALDC camera was caused by decentering distortion. Second, we compared the accuracy of bundle adjustment for camera calibration using three image types: raw imagery without the ALDC option; imagery corrected using lens profiles; and imagery with the ALDC option. The results of image triangulation, the digital terrain model (DTM), and the orthoimage using the IO parameters for the ALDC camera were similar to or slightly better than the results using self-calibration. These results confirm that the ALDC camera can be used in a photogrammetric UAV system using only self-calibration.

A Design Method for Pre-Distortion Compensation of SAR Chirp Signal based on Envelop Sampling and Interpolation Filter (위성 탑재 영상레이다 첩 신호의 전치왜곡 보상을 위한 포락선 샘플링 및 보간 필터 기반의 설계 기법)

  • Lee, Young-Bok
    • Journal of the Korea Institute of Military Science and Technology
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    • v.25 no.4
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    • pp.347-354
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    • 2022
  • The synthetic aperture radar(SAR) is an equipment that can acquire images in all weathers day and night based on radar signals. The on-board processor of satellite SAR generates transmission signal by digital signal processing, converts it into an analog signal and transmits to antenna. Until the transmission signal generated by on-board processor is output, the signal passes the transmission cables and analog devices. At this time, these hardware distort the signal and makes SAR performance worse. To improve the performance, pre-distortion technique is used. But, general pre-distortion using taylor series is not sufficient to compensate for the distortion. This paper suggests transmit signal design method with improved pre-distortion. This paper uses envelop sampling method and interpolation filter for frequency domain compensation. The proposed method accurately compensates the hardware distortion and reduces resource usage of FPGA. To analyze proposed method's performance, IRF characteristics are compared when the proposed method applies to signal with errors.

Digital Predistortion for Closely Spaced Dual-Band Signals (근접한 이중대역 신호에 대한 디지털 전치왜곡 기법)

  • Jeong, Eui-Rim;Oh, Joo-Hyun;Kim, Do-Kyoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.12
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    • pp.1684-1690
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    • 2018
  • A new digital pre-distortion (DPD) technique for closely spaced dual-band signals is proposed. In the system under consideration, dual-band signals are amplified by a single broadband power amplifier (PA) at a transmitter. The PA output is distorted by cross-modulation between the two bands as well as their own inter-modulation distortion. Especially, if the two bands are placed in close proximity to each other, their spectral regrowths due to in-band intermodulation overlap with each other, which degrades DPD performance. To solve this problem, we propose a new DPD technique where the dual-band PA characteristics are estimated first, and then the DPD parameters are obtained from the estimated PA characteristics. By finding the DPD parameters through two steps, pre-distortion can perform well for the closely-spaced dual band signals. The proposed technique is verified through computer simulation. Simulation result shows that the proposed method performs better than the conventional method for closely-spaced dual band signals.

The Development of the Data Error Inspection Algorithm for the Remote Sensing by Wireless Communication (원격계측을 위한 무선 통신 에러 검사 알고리즘 개발)

  • 김희식;김영일;설대연;남철
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2004.10a
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    • pp.993-997
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    • 2004
  • A data error inspection algorithm for wireless digital data communication was developed. Original data converted By wireless digital data error inspection algorithm. Wireless digital data is high possibility to get distortion and lose by noise and barrier on wireless. If the data check damaged and lost at receiver, can't make it clear and can't judge whether this data is right or not. Therefore, by wireless transmission data need the data error inspection algorithm in order to decrease the data distortion and lose and to monitoring the transmission data as real time. This study consists of RF station for wireless transmission, Water Level Meter station for water level measurement and Error inspection algorithm for error check of transmission data. This study is also that investigation and search for error inspection algorithm in order to wireless digital data transmission in condition of the least data's damage and lose. Designed transmitter and receiver with one - chip micro process to protect to swell the volume of circuit. Had designed RF transmitter - receiver station simply by means of ATMEL one - chip micro processing the systems. Used 10mW of the best RF power and 448MHz-449MHz on frequency band which is open to public touse free within the limited power.

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Design of 3V a Low-Power CMOS Analog-to-Digital Converter (3V 저전력 CMOS 아날로그-디지털 변환기 설계)

  • 조성익;최경진;신홍규
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.11
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    • pp.10-17
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    • 1999
  • In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

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Design of Digital Peaking Filters Using Q-Compensation (Q-보정을 이용한 디지털 픽킹 필터 설계)

  • 이지하;이규하;박영철;안동순;윤대희
    • The Journal of the Acoustical Society of Korea
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    • v.19 no.3
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    • pp.63-71
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    • 2000
  • A new type of second-order digital peaking filters for professional-quality digital audio system is proposed whose frequency response can be elaborately controlled throughout the composite structure of a standard band-pass filter and a 0-dB bypass gain. The proposed method for designing the peaking filter uses the Q-compensation technique to prevent the Q-distortion caused by the variation of the gain factor and is reduced into a compact form which is proper to the real-time implementation. Methods are examined for computing its coefficients, which are exact and very straightforward to compute with small amount of the system resources.

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Scheme to Improve the Line Current Distortion of PFC Using a Predictive Control Algorithm

  • Kim, Dae Joong;Park, Jin-Hyuk;Lee, Kyo-Beum
    • Journal of Power Electronics
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    • v.15 no.5
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    • pp.1168-1177
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    • 2015
  • This paper presents a scheme to improve the line current distortion of power factor corrector (PFC) topology at the zero crossing point using a predictive control algorithm in both the continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The line current in single-phase PFC topology is distorted at the zero crossing point of the input AC voltage because of the characteristic of the general proportional integral (PI) current controller. This distortion degrades the line current quality, such as the total harmonic distortion (THD) and the power factor (PF). Given the optimal duty cycle calculated by estimating the next state current in both the CCM and DCM, the proposed predictive control algorithm has a fast dynamic response and accuracy unlike the conventional PI current control method. These advantages of the proposed algorithm lower the line current distortion of PFC topology. The proposed method is verified through PSIM simulations and experimental results with 1.5 kW bridgeless PFC (BLPFC) topology.