• ETRI Journal
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• v.36 no.2
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• pp.206-213
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• 2014

This paper presents a novel 90 GHz band 16-quadrature amplitude modulation (16-QAM) orthogonal frequency-division multiplexing (OFDM) communication system. The system can deliver 6 Gbps through six channels with a bandwidth of 3 GHz. Each channel occupies 500 MHz and delivers 1 Gbps using 16-QAM OFDM. To implement the system, a low-noise amplifier and an RF up/down conversion fourth-harmonically pumped mixer are implemented using a $0.1-{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor process. A polarization-division duplex architecture is used for full-duplex communication. In a digital modem, OFDM with 256-point fast Fourier transform and (255, 239) Reed-Solomon forward error correction codecs are used. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 19.8 dB.

• ETRI Journal
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• v.34 no.5
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• pp.649-654
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• 2012

This paper presents a novel 16-quadrature-amplitude-modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a $0.1{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 21.5 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.197-202
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• 2010

In this paper, multi-channel vital signal monitoring system was implemented for home healthcare. The system able to measure vital signal for example ECG, PPG and temperature simultaneously at patients’ home. The vital signal is an essential parameter for healthcare application and can be easily extracted from patients. The implemented system consist of sensor parts for signal extraction, signal amplifier and filter for analog circuit, analog signal to digital conversion for controlling devices and lastly the monitoring program. The system able to transmit vital signals using Bluetooth wireless communications to personal computer or home server. And the tele-monitoring system able to display real-time signals using web monitoring program. In medical application, the vital signal parameter able to stored and saved in the web server for further medical analysis. This system opens up the possibilities of ubiquitous healthcare where further implementation can be easily done.

• Journal of Biomedical Engineering Research
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• v.22 no.6
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• pp.503-510
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• 2001

In this paper. we describe a 32-channel bioimpedance measurement system It consists of 32 independent constant current sources of 50 kHz sinusoid. The amplitude of each current source can be adjusted using a 12-bit MDAC. After we applied a pattern of injection currents through 32 current injection electrodes. we measured induced boundary voltages using a variable-gain narrow-band instrumentation amplifier. a Phase-sensitive demodulator. and a 12-bit ADC. The system is interfaced to a PC for the control and data acquisition. We used the system to detect anomalies with different resistivity values in a saline Phantom with 290mm diameter The accuracy of the developed system was estimated as 2.42% and we found that anomalies larger than 8mm in diameter can be detected. We Plan to improve the accuracy by using a digital oscillator improved current sources by feedback control, Phase-sensitive A/D conversion. etc. to detect anomalies smaller than 1mm in diameter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.179-189
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• 2000

Recently, due to the increasing interests in deep sea development, all possible efforts to the development of underwater unmanned working vehicles such as AUV(Autonomous Underwater Vehicle) or underwater robot are exerted. This paper proposes a new efficient acoustic-based underwater image data communication system, which ensures a certain level of maximum throughput regardless of the propagation delay of ultrasonic and allowsfast data transmission through the multiple ultrasonic communication channel. Proposed system consists of an acoustic transducer which operates at 136kHz center frequency and it's 10kHz bandwidth, pre-amplifier, $\pi/4 QPSK$(Quadrature Phase Shift Keying) modulation/demodu-lation method, image compressing method using JPEG technique and modified Stop & Wait protocol. The experimental result of the system make it possible to transfer the underwater image as a high throughput at the basin test. The results of test are also verified which allows to desirable transmission performance compared with the existing developed system and the possibility to put the practical use of survey and investigation in the water.

• Journal of IKEEE
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• v.25 no.1
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• pp.156-167
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• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.5
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• pp.547-555
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• 2008

This parer proposed the path mismatch detection and compensation algorithm with closed form for linear amplification with non-linear components(LINC) system implementation. The LINC system has a merit of using the high efficient amplifier by transferring the non-constant envelop signal which is high peak to average signal ratio into constant envelop signal. However, the performance degradation is very sensitive to the path mismatch such as an amplitude mismatch and a phase mismatch. In order to improve the path mismatch, the error detection and compensation method is introduced by the use of four test signals. Since the presented method has the closed form solution, the efficient and fast detection is available. The digital-IF structure of LINC system applied by the proposed error detection and compensation algorithm was implemented. The performance was evaluated with the IEEE 802.16 WiMAX baseband sinal which has 7 MHz channel bandwidth and 16-QAM. The Error Vector Magnitude(EVM) of -37.37 dB was obtained through performance test, which meets performance requirement of -24 dB EVM. As a result, the introduced error detection and compensation method was verified to improve the LINC system performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.