• Journal of the Korean Society for Nondestructive Testing
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• v.33 no.5
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• pp.465-471
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• 2013

A steam generator in nuclear power plant is a heatexchager which is used to convert water into steam from heat produced in a nuclear reactor core, and the steam produced in steam generator is delivered to the turbine to generate electricity. Because of damage to steam generator tubing may impair its ability to adequately perform required safety functions in terms of both structural integrity and leakage integrity, eddy current testing is periodically performed to evaluate the integrity of tubes in steam generator. This assessment is normally performed during a reactor refueling outage. Currently, the eddy current testing for steam generator of nuclear power plant in Korea is performed in accordance with KEPIC & ASME Code requirements, the eddy current testing system is consists of remote data acquisition unit and data analysis program to evaluate the acquired data. The KEPIC & ASME Code require that the electrical properties of remote data acquisition unit, such as total harmonic distortion, input & output impedance, amplifier linearity & stability, phase linearity, bandwidth & demodulation filter response, analog-to-digital conversion, and channel crosstalk shall be measured in accordance with the KEPIC & ASME Code requirements. In this paper, the measurement requirements of electrical properties for eddy current testing instrument described in KEPIC & ASME Code are presented, and the measurement results of newly developed eddy current testing instrument by KHNP(Korea Hydro & Nuclear Power Co., LTD) are presented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.