• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.834-845
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• 2011

Massive broadcasting contents such as UHD(Ultra High Definition) TV which requires multi-channel capacity for transmission has been introduced in recent years. A transmission scheme with channel bonding has been considered for transmission of massive broadcasting contents. In HFC(Hybrid Fiber Coaxial) networks, DOCSIS 3.0(Data Over Cable Service Interface Specification 3.0) has already applied channel bonding schemes for up/downstream of data service. A method unlike DOCSIS 3.0 is required to introduce a channel bonding scheme in the broadcasting service having unidirectional transmission with a downstream. Since a massive broadcasting content requires several channels for transmission, VBR(Variable Bit Rate) transmission has been emerging for the bandwidth efficiency. In addition, research on channel allocation and resource scheduling is required to guarantee QoS(Quality of Service) for the broadcasting service based on VBR. In this paper, we propose a transmission method for mass broadcasting service in HFC network and show the UHD transmission simulator developed to evaluate the performance. In order to evaluate the performance, we define various scenarios. Using the simulator, we assess the possibility of channel bonding and VBR transmission for UHD broadcasting system to provide mass broadcasting service efficiently. The developed simulator is expected to contribute to the efficient transmission system development of mass broadcasting service.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.