• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.5
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• pp.401-406
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• 2005

Digital memory circuits have been developed very fast according to the progress of semiconductor technology. But it was very difficult to memorize a wideband radio frequency signals. Many years ago, an analog frequency memory loop(FML) was used for store of radio frequency signal and the digital radio frequency memory was made according to the development of wideband amplifier and high speed sampler. We present a design of wideband digital radio frequency reproduction device using ladder circuit and the simulation results with respect to the sampling speed in this paper.

• Proceedings of the Korea Contents Association Conference
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• 2004.05a
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• pp.372-376
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• 2004

Digital memory circuits have been developed very fast according to the progress of semiconductor technology But It was very difficult to memorize a high frequency radio signal. Many years ago an analog loop was used for store of radio frequency signal, and the digital radio frequency memory was made to the development of wideband amplifier and high speed sampler. We present a design of wide-band DRFM using Johnson code and the simulation results with respect to the sampling speed. in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.507-511
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• 2010

Digital Radio Frequency Memory (below, DRFM) performs RF signal data store, delay and re-transmission. DRFM is wildly used as core module of Jammer, EW simulator, Target Echo Generator etc. This paper suggests a hardware design of DRFM which is composed RF section(RF Input/Output Module, Local Oscillator Module) and Digital section(ADC module, memory, DAC module), and confirm the validity of the propose by the test result.

• Journal of electromagnetic engineering and science
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• v.1 no.2
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• pp.131-138
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• 2001

The DTV (Digital TV) tuner for an 8-VSB (Vestigial Side-Band) modulation was developed to meet the requirements of the ATSC (Advanced Television Systems Committee). The double frequency conversion and the active tracking filter in the front-end were used to cancel interferences between adjacent channels and multi-channels by suppressing the IF beat and the Image frequency. However, It was impossible to get frequency mapping between the tracking filter and the first VCO (Voltage Controlled Oscillator) in the existing DTV tuner structure which differs from the NTSC (National Television Systems Committee) tuner. This paper, therefore, suggests an assailable structure and a new method for the automatic frequency selection by mapping the frequency characteristics over the tracking voltage and the combined HW which is composed of a Micro-controller, an EEPROM (Electrically Erasable Programmable Read Only Memory), a DAC (Digital-to-Analog Converter), an OP amplifier, and a switch driver.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2164-2170
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• 2010

Digital Radio Frequency Memory, ( as DRFM ), is a device with the ability to restore output to the input RF signal in the required time after storing the incoming RF signals. Therefore DRFM is widely used in Jammer, EW Simulator, Target Echo Generator, and so on. This paper proposes its hardware implementation composed with the high frequency part and the digital processing part consisting of RF input/output module and local oscillator module. It is also proposed the replicated signal generation method which is consisted of the Analog-Digital conversion in the form of pulsed RF signal quantization, and FPGA to save and produce the playback signal, and RF signals to produce a Digital-Analog Conversion in the digital processing unit. This proposed scheme applied to test board and confirmed the validity of the proposed scheme through the test results obtained by the simulated input signals.

• Journal of electromagnetic engineering and science
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• v.11 no.3
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• pp.213-219
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• 2011

Simulative target generators are needed for testing and calibrating various radar systems. The generator in this study discriminates the transmitting frequency from a radar and simulates parameters like target range, range rate, and atmospheric attenuation using the digital RF memory technique. The simulative target echo is then sent to the radar for testing and evaluation. This paper proposes a novel architecture for controlling the digital RF memory so it continually writes ADC data to the memory and reads it for the DAC with increasing one step address in order to control the delay of target range in a simple way. The target echo is programmed according to various preprogrammed scenarios and is generated in real time using a wireless local area network (LAN). To analyze the detected and generated target information easily, the system times for the radar and simulative target generator are synchronized using a global positioning system (GPS).

• Journal of Convergence for Information Technology
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• v.9 no.8
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• pp.134-139
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• 2019

This paper describes the effect of multiple signal regeneration in quadrature digital radio frequency memory(DRFM). Single channel DRFM have good reproducibility after storing a single signal. However, when reproduced after storing multiple signals, the spurious signal is large. The quadrature DRFM consists of I and Q channels, which can greatly reduce the spurious signal. The amplitude of the spurious signal depends on the number of bits of data stored in the DRFM. In this paper, we have obtained the number of bits of signal regeneration according to the application of radio frequency memory by obtaining the size of the spurious signal according to the number of bits of the stored data of the DRFM for multiple signals. As a result of this study, 4 bits quadrature DRFM can achieve a spurious output of less than -20dB, which is used for 4 signals. Those are expected to greatly contribute to the signal analysis of electronic warfare equipment and the development of jamming device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.7
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• pp.955-961
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• 2021

In modern warfare, the importance of electronic warfare, which carries out a mission that using radio wave to find out enemy information or to protect ally information, has increased. Radar jamming technique is one of the most representative techniques of EA(Electronic Attack), it disturbs and deceives enemy radar system in order to secure ally location information. Velocity deception jamming technique, which is one of the radar jamming techniques, generally operate against pulse-doppler radar which use doppler effect in order to track target's velocity and location. Velocity Deception Jamming Technique can be implemented using DRFM(Digital Radio Frequency Memory) that performs Frequency Modulation. In this paper, I describe implementation method of VGPO/VGPI(Velocity Gate Pull-Off/Pull-In) velocity deception jamming technique using phase-sampled DRFM, and verify the operation of VGPO/VGPI velocity deception jamming technique with board test under signal injection condition.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1213-1221
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• 2022

In Electronic Warfare, the need to develop a jamming system that protects our location information from enemy radar is constantly increasing. The jamming system normally uses wide-band DRFM(Digital Radio Frequency Memory) that processes the entire bandwidth at once. However, it is difficult to jam if there is a CW(Continuous Wave) interference signal in the band. Recently, instead of wide-band signal processing, a structure using a filter bank that divides the entire band into several sub-bands and processes each sub-band independently has been proposed. Although it is possible to handle interference signal through the filter bank structure, spurious signal occurs when the signal is received at a boundary frequency between sub-bands. Spurious signal makes a output power of jamming signal distributed, resulting in lower JSR(Jamming to Signal Ratio) and less jamming effect. This paper proposes an over-sampled channelized DRFM structure that enables interference response and prevents spurious signal for sub-band boundary frequency input.

• The KIPS Transactions:PartC
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• v.12C no.7 s.103
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• pp.965-972
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• 2005

Digital documents have become the mainstay of the paperless office. This is due to the increased usage of computer networks and the widespread digital culture. Along with the increased usage of digital documents comes the problem of securing them. The documents nay have very important information such as confidential business policies and intellectual Property statements. Generally, most of users protect them by using a password or secured flash memory or security software, but it has several weaknesses. Accordingly, we propose a new architecture for securing digital documents. The proposed architecture bases on RFID and several encrypting techniques. It makes up for the weakness of traditional securing architectures, and supports various Policies for digital documents of users.